Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58896 )
Change subject: ChromeOS: Add legacy mainboard_ec_running_ro() ......................................................................
ChromeOS: Add legacy mainboard_ec_running_ro()
Motivation is to have mainboard_chromeos_acpi_generate() do nothing else than fill ACPI \OIPG package.
Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58896 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Julius Werner jwerner@chromium.org --- M src/include/bootmode.h M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c 7 files changed, 34 insertions(+), 29 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/include/bootmode.h b/src/include/bootmode.h index da2dbf6..e2d1cb9 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -3,6 +3,8 @@ #ifndef __BOOTMODE_H__ #define __BOOTMODE_H__
+#include <stdbool.h> + /* functions implemented per mainboard: */ void init_bootmode_straps(void); int get_write_protect_state(void); @@ -12,6 +14,7 @@ int get_wipeout_mode_switch(void); int get_lid_switch(void); int get_ec_is_trusted(void); +bool mainboard_ec_running_ro(void);
/* Return 1 if display initialization is required. 0 if not. */ int display_init_required(void); diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index a7d56ae..fb249d4 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -48,6 +48,15 @@ return 0; }
+bool mainboard_ec_running_ro(void) +{ + // TODO: MLR + // The firmware read/write status is a "virtual" switch and + // will be handled elsewhere. Until then hard-code to + // read/write instead of read-only for developer mode. + return false; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), @@ -55,13 +64,6 @@
void mainboard_chromeos_acpi_generate(void) { - // TODO: MLR - // The firmware read/write status is a "virtual" switch and - // will be handled elsewhere. Until then hard-code to - // read/write instead of read-only for developer mode. - if (CONFIG(CHROMEOS_NVS)) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); }
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 2b361ac..e0bc0b0 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -46,7 +46,7 @@ return !get_gpio(GPIO_REC_MODE); }
-static int parrot_ec_running_ro(void) +bool mainboard_ec_running_ro(void) { return get_recovery_mode_switch(); } @@ -58,9 +58,6 @@
void mainboard_chromeos_acpi_generate(void) { - if (CONFIG(CHROMEOS_NVS) && !parrot_ec_running_ro()) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); }
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 964217e..fcbbc8a 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -49,8 +49,7 @@ * The recovery-switch is virtual on Stout and is handled via the EC. * Stout recovery mode is only valid if RTC_PWR_STS is set and the EC * indicated the recovery keys were pressed. We use a global flag for - * rec_mode to be used after RTC_POWER_STS has been cleared. This function - * is complicated by romstage support, which can't use a global variable. + * rec_mode to be used after RTC_POWER_STS has been cleared. * Note, rec_mode is the only time the EC is in RO mode, otherwise, RW. */ int get_recovery_mode_switch(void) @@ -75,6 +74,11 @@ return ec_in_rec_mode; }
+bool mainboard_ec_running_ro(void) +{ + return !!get_recovery_mode_switch(); +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), @@ -82,8 +86,5 @@
void mainboard_chromeos_acpi_generate(void) { - if (CONFIG(CHROMEOS_NVS) && !get_recovery_mode_switch()) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 22b936c..1b9c7c4 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -85,6 +85,11 @@ pci_s_write_config32(dev, SATA_SP, flags); }
+bool mainboard_ec_running_ro(void) +{ + return !ec_read(0xcb); +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), @@ -92,8 +97,5 @@
void mainboard_chromeos_acpi_generate(void) { - if (CONFIG(CHROMEOS_NVS) && ec_read(0xcb)) - chromeos_set_ecfw_rw(); - chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); } diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index abdd6c2..da25617 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -25,7 +25,6 @@ void cbmem_add_vpd_calibration_data(void); void chromeos_set_me_hash(u32*, int); void chromeos_set_ramoops(void *ram_oops, size_t size); -void chromeos_set_ecfw_rw(void); void chromeos_init_chromeos_acpi(void);
/** diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 7821786..b1090a4 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -2,6 +2,7 @@
#include <acpi/acpi.h> #include <acpi/acpigen.h> +#include <bootmode.h> #include <types.h> #include <string.h> #include <stdlib.h> @@ -31,6 +32,8 @@ return region_device_sz(&vpd); }
+__weak bool mainboard_ec_running_ro(void) { return true; } + void chromeos_init_chromeos_acpi(void) { size_t vpd_size; @@ -59,8 +62,13 @@ /* EC can override to ECFW_RW. */ chromeos_acpi->vbt2 = ACTIVE_ECFW_RO;
- if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_ec_running_ro()) - chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (!google_ec_running_ro()) + chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; + } else { + if (!mainboard_ec_running_ro()) + chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; + } }
void chromeos_set_me_hash(u32 *hash, int len) @@ -83,13 +91,6 @@ chromeos_acpi->ramoops_len = size; }
-void chromeos_set_ecfw_rw(void) -{ - if (!chromeos_acpi) - return; - chromeos_acpi->vbt2 = ACTIVE_ECFW_RW; -} - void smbios_type0_bios_version(uintptr_t address) { if (!chromeos_acpi)
-
Kyösti Mälkki (Code Review)