[S] Change in coreboot[main]: soc/intel/adl: Handle critical low battery early in romstage

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik.

Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86227?usp=email )

Change subject: soc/intel/adl: Handle critical low battery early in romstage
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Patch Set 3:

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/86227/comment/f03fc3fb_7f8dd273?usp... :
PS3, Line 446: 			early_shutdown_if_battery_below_critical_threshold();
> Why is this inserted here? Isn't this the code path that only happens when MRC cache data was not fo […]

I think the motivation is to inform the user as much as possible through Graphical UI than text. That is why the text based notification is limited only when the memory training is required. If we do it in romstage entry, then we will most likely end with the text based notification all the time.