Change in coreboot[master]: mb/intel/adlrvp: Enable eMMC device for ADL-N RVP

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61130 )

Change subject: mb/intel/adlrvp: Enable eMMC device for ADL-N RVP
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mb/intel/adlrvp: Enable eMMC device for ADL-N RVP

Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder
Lake N RVP from devicetree.

Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab
Signed-off-by: Krishna Prasad Bhat 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130
Tested-by: build bot (Jenkins) 
Reviewed-by: Rizwan Qureshi 
Reviewed-by: Ronak Kanabar 
Reviewed-by: Usha P 
Reviewed-by: Maulik V Vaghela 
---
M src/mainboard/intel/adlrvp/devicetree_n.cb
M src/mainboard/intel/adlrvp/gpio_n.c
2 files changed, 31 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Rizwan Qureshi: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, approved
  Ronak Kanabar: Looks good to me, approved
  Usha P: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
index 0dea803..f7da2d1 100644
--- a/src/mainboard/intel/adlrvp/devicetree_n.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -16,6 +16,9 @@
    # Sagv Configuration
    register "SaGv" = "SaGv_Enabled"

+	# eMMC HS400
+	register "emmc_enable_hs400_mode" = "1"
+
    register "usb2_ports[0]" = "USB2_PORT_MID(OC3)"		# Type-C Port1
    register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"		# Type-C Port2
    register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# FPS connector
@@ -276,6 +279,7 @@
    	device ref uart0 on end
    	device ref gspi0 on end
    	device ref p2sb on end
+		device ref emmc on end
    	device ref hda on
    		chip drivers/intel/soundwire
    			device generic 0 on
diff --git a/src/mainboard/intel/adlrvp/gpio_n.c b/src/mainboard/intel/adlrvp/gpio_n.c
index 9ba20ba..6f4e4a5 100644
--- a/src/mainboard/intel/adlrvp/gpio_n.c
+++ b/src/mainboard/intel/adlrvp/gpio_n.c
@@ -42,6 +42,33 @@
    /* M2_SSD_DEVSLP */
    PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),

+	/* I5  : NC */
+	PAD_NC(GPP_I5, NONE),
+	/* I7  : EMMC_CMD ==> EMMC_CMD */
+	PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+	/* I8  : EMMC_DATA0 ==> EMMC_D0 */
+	PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+	/* I9  : EMMC_DATA1 ==> EMMC_D1 */
+	PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
+	/* I10 : EMMC_DATA2 ==> EMMC_D2 */
+	PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
+	/* I11 : EMMC_DATA3 ==> EMMC_D3 */
+	PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
+	/* I12 : EMMC_DATA4 ==> EMMC_D4 */
+	PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
+	/* I13 : EMMC_DATA5 ==> EMMC_D5 */
+	PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
+	/* I14 : EMMC_DATA6 ==> EMMC_D6 */
+	PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
+	/* I15 : EMMC_DATA7 ==> EMMC_D7 */
+	PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
+	/* I16 : EMMC_RCLK ==> EMMC_RCLK */
+	PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
+	/* I17 : EMMC_CLK ==> EMMC_CLK */
+	PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
+	/* I18 : EMMC_RESET# ==> EMMC_RST_L */
+	PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
+
    /* TYPEA_CONN23_USB2_P8_OC1_N */
    PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
    /* CRD1_PWREN */