Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...

[Tim Crawford (Code Review)]

Attention is currently required from:  Felix Singer, Tim Crawford, Jeremy Soller.
Hello build bot (Jenkins), Nico Huber, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/49104

to look at the new patch set (#5).

Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
......................................................................

soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit

Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.

A description of this behavior, along with example code, is provided in
the TigerLake FSP Integration Guide.

The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.

Tested by checking lspci output on System76 galp3-c, oryp5, oryp6.

References:
- TigerLake FSP Integration Guide
- Intel Document Number 337868-002

Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e
Signed-off-by: Jeremy Soller 
Signed-off-by: Tim Crawford 
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/49104/5