[S] Change in coreboot[main]: soc/qualcomm/{sc7180,sc7280}: Use correct return types for functions

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79015?usp=email )

Change subject: soc/qualcomm/{sc7180,sc7280}: Use correct return types for functions
......................................................................

soc/qualcomm/{sc7180,sc7280}: Use correct return types for functions

Some functions in the headers for sc7180 and sc7280 specified the
int as their return type when they should have used enum cb_err.
Found while testing GCC 13.2.0

Change-Id: I41331fe708a396f7f2f40359e8ba03c8a46a4d4b
Signed-off-by: Zebreus 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79015
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Singer 
Reviewed-by: Julius Werner 
---
M src/soc/qualcomm/sc7180/include/soc/clock.h
M src/soc/qualcomm/sc7280/include/soc/clock.h
2 files changed, 6 insertions(+), 6 deletions(-)

Approvals:
  Julius Werner: Looks good to me, approved
  build bot (Jenkins): Verified
  Felix Singer: Looks good to me, approved

diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h
index 4e80fe8..4541ecb 100644
--- a/src/soc/qualcomm/sc7180/include/soc/clock.h
+++ b/src/soc/qualcomm/sc7180/include/soc/clock.h
@@ -195,7 +195,7 @@
 void clock_configure_qup(int qup, uint32_t hz);
 void clock_enable_qup(int qup);
 void clock_configure_dfsr(int qup);
-int mdss_clock_configure(enum mdss_clock clk_type, uint32_t source,
+enum cb_err mdss_clock_configure(enum mdss_clock clk_type, uint32_t source,
    		uint32_t divider, uint32_t m, uint32_t n, uint32_t d);
 int mdss_clock_enable(enum mdss_clock clk_type);

diff --git a/src/soc/qualcomm/sc7280/include/soc/clock.h b/src/soc/qualcomm/sc7280/include/soc/clock.h
index d22ba37..402c898 100644
--- a/src/soc/qualcomm/sc7280/include/soc/clock.h
+++ b/src/soc/qualcomm/sc7280/include/soc/clock.h
@@ -383,14 +383,14 @@
 void clock_configure_sdcc1(uint32_t hz);
 void clock_configure_sdcc2(uint32_t hz);
 void clock_configure_dfsr(int qup);
-int clock_enable_gdsc(enum clk_gdsc gdsc_type);
+enum cb_err clock_enable_gdsc(enum clk_gdsc gdsc_type);

-int mdss_clock_configure(enum clk_mdss clk_type, uint32_t hz,
+enum cb_err mdss_clock_configure(enum clk_mdss clk_type, uint32_t hz,
    		uint32_t source, uint32_t divider,
    		uint32_t m, uint32_t n, uint32_t d);
-int mdss_clock_enable(enum clk_mdss clk_type);
-int clock_enable_pcie(enum clk_pcie clk_type);
-int clock_configure_mux(enum clk_pcie clk_type, u32 src_type);
+enum cb_err mdss_clock_enable(enum clk_mdss clk_type);
+enum cb_err clock_enable_pcie(enum clk_pcie clk_type);
+enum cb_err clock_configure_mux(enum clk_pcie clk_type, u32 src_type);

/* Subsystem Reset */
 static struct aoss *const aoss = (void *)AOSS_CC_BASE;