Change in coreboot[master]: mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41198 )

Change subject: mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU
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mb/google/hatch: Modify the puff fmd files to support CSE Lite SKU

This patch modified the puff fmd files to support CSE Lite SKU.
* Reduce the SI_ALL size to  3MiB since ME binary size is less
  than 2.5MiB.
* Increase the FW_MAIN_A/B size to accommodate the ME_RW update
  binary with CSE Lite SKU.

BUG=b:154561163
TEST=Build and boot puff with CSE Lite SKU.
Cq-Depend: chrome-internal:3046770

Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c
Signed-off-by: V Sowmya 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41198
Reviewed-by: Sridhar Siricilla 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/hatch/chromeos-puff-16MiB.fmd
M src/mainboard/google/hatch/chromeos-puff-32MiB.fmd
2 files changed, 23 insertions(+), 23 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Sridhar Siricilla: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd b/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd
index 9f09819..61a0b0f 100644
--- a/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd
+++ b/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd
@@ -1,20 +1,20 @@
 FLASH@0xff000000 0x1000000 {
-	SI_ALL@0x0 0x400000 {
+	SI_ALL@0x0 0x300000 {
    	SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x3ff000
+		SI_ME@0x1000 0x2ff000
    }
-	SI_BIOS@0x400000 0xc00000 {
-		RW_SECTION_A@0x0 0x368000 {
+	SI_BIOS@0x300000 0xd00000 {
+		RW_SECTION_A@0x0 0x3e8000 {
    		VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x357fc0
-			RW_FWID_A@0x367fc0 0x40
+			FW_MAIN_A(CBFS)@0x10000 0x3d7fc0
+			RW_FWID_A@0x3e7fc0 0x40
    	}
-		RW_SECTION_B@0x368000 0x368000 {
+		RW_SECTION_B@0x3e8000 0x3e8000 {
    		VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x357fc0
-			RW_FWID_B@0x367fc0 0x40
+			FW_MAIN_B(CBFS)@0x10000 0x3d7fc0
+			RW_FWID_B@0x3e7fc0 0x40
    	}
-		RW_MISC@0x6D0000 0x30000 {
+		RW_MISC@0x7d0000 0x30000 {
    		UNIFIED_MRC_CACHE@0x0 0x20000 {
    			RECOVERY_MRC_CACHE@0x0 0x10000
    			RW_MRC_CACHE@0x10000 0x10000
@@ -29,8 +29,8 @@
    		RW_SPD_CACHE(PRESERVE)@0x2f000 0x1000
    	}
    	# RW_LEGACY needs to be minimum of 1MB
-		RW_LEGACY(CBFS)@0x700000 0x100000
-		WP_RO@0x800000 0x400000 {
+		RW_LEGACY(CBFS)@0x800000 0x100000
+		WP_RO@0x900000 0x400000 {
    		RO_VPD(PRESERVE)@0x0 0x4000
    		RO_SECTION@0x4000 0x3fc000 {
    			FMAP@0x0 0x800
diff --git a/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd b/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd
index 37bc1bd..81840b1 100644
--- a/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd
+++ b/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd
@@ -1,24 +1,24 @@
 FLASH@0xfe000000 0x2000000 {
-	SI_ALL@0x0 0x400000 {
+	SI_ALL@0x0 0x300000 {
    	SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x3ff000
+		SI_ME@0x1000 0x2ff000
    }
-	SI_BIOS@0x400000 0x1c00000 {
+	SI_BIOS@0x300000 0x1d00000 {
    	# Place RW_LEGACY at the start of BIOS region such that the rest
    	# of BIOS regions start at 16MiB boundary. Since this is a 32MiB
    	# SPI flash only the top 16MiB actually gets memory mapped.
    	RW_LEGACY(CBFS)@0x0 0x1000000
-		RW_SECTION_A@0x1000000 0x3e0000 {
+		RW_SECTION_A@0x1000000 0x460000 {
    		VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x3cffc0
-			RW_FWID_A@0x3dffc0 0x40
+			FW_MAIN_A(CBFS)@0x10000 0x44ffc0
+			RW_FWID_A@0x45ffc0 0x40
    	}
-		RW_SECTION_B@0x13e0000 0x3e0000 {
+		RW_SECTION_B@0x1460000 0x460000 {
    		VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x3cffc0
-			RW_FWID_B@0x3dffc0 0x40
+			FW_MAIN_B(CBFS)@0x10000 0x44ffc0
+			RW_FWID_B@0x45ffc0 0x40
    	}
-		RW_MISC@0x17c0000 0x40000 {
+		RW_MISC@0x18c0000 0x40000 {
    		UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
    			RECOVERY_MRC_CACHE@0x0 0x10000
    			RW_MRC_CACHE@0x10000 0x20000
@@ -34,7 +34,7 @@
    	}
    	# Make WP_RO region align with SPI vendor
    	# memory protected range specification.
-		WP_RO@0x1800000 0x400000 {
+		WP_RO@0x1900000 0x400000 {
    		RO_VPD(PRESERVE)@0x0 0x4000
    		RO_SECTION@0x4000 0x3fc000 {
    			FMAP@0x0 0x800