Change in coreboot[master]: soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50405 )

Change subject: soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number
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soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number

Signed-off-by: Felix Held 
Change-Id: Id9042def0f5e9d2fa994d6729c592c7e2152976b
---
M src/soc/amd/stoneyridge/cpu.c
1 file changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/50405/1

diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index c898ff7..9992fc5 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -16,6 +16,7 @@
 #include <soc/smi.h>
 #include <soc/iomap.h>
 #include <console/console.h>
+#include <amdblocks/psp.h>

/*
  * MP and SMM loading initialization.
@@ -121,10 +122,10 @@
    uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
    psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
    psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
-	psp_msr = rdmsr(0xc00110a2);
+	psp_msr = rdmsr(MSR_PSP_ADDR);
    if (psp_msr.lo == 0) {
    	psp_msr.lo = psp_bar;
-		wrmsr(0xc00110a2, psp_msr);
+		wrmsr(MSR_PSP_ADDR, psp_msr);
    }
 }