Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28464 )

Change subject: drivers/intel/fsp1_1: Configure UART after memory init
......................................................................

drivers/intel/fsp1_1: Configure UART after memory init

FSP code will default enable the onboard serial port.
When external serial port is used, this onboard port needs to be
disabled.

Add function mainboard_after_memory_init() function to perform
required actions to re-enabled output to external serial port.

BUG=N/A
TEST=LPC Post card on Intel Cherry Hill

Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Signed-off-by: Frans Hendriks 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M src/drivers/intel/fsp1_1/include/fsp/romstage.h
M src/drivers/intel/fsp1_1/raminit.c
2 files changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index e266bee..d608484 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2014 Google Inc.
  * Copyright (C) 2015-2016 Intel Corporation
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -91,5 +92,6 @@
 /* Update the SOC specific memory config param for mma. */
 void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
    	struct mma_config_param *mma_cfg);
+void mainboard_after_memory_init(void);

#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 2dd5c77..8405c94 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -125,6 +125,7 @@
    timestamp_add_now(TS_FSP_MEMORY_INIT_START);
    post_code(POST_FSP_MEMORY_INIT);
    status = fsp_memory_init(&fsp_memory_init_params);
+	mainboard_after_memory_init();
    post_code(0x37);
    timestamp_add_now(TS_FSP_MEMORY_INIT_END);

@@ -322,3 +323,9 @@
 {
    printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+/* Initialize the SoC after MemoryInit */
+__weak void mainboard_after_memory_init(void)
+{
+	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}