[L] Change in coreboot[main]: soc/xeon_sp: Initially add N-1 IBL codes

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81315?usp=email )

Change subject: soc/xeon_sp: Initially add N-1 IBL codes
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Patch Set 8:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81315/comment/3c3d1c11_00b72abb :
PS6, Line 9: IBL
> Please reference the intel documents used to write this code and give a short introduction what the  […]

This is a N-1 stubbed codes forked from previous generation and hence we cannot refer to a document ID for this as of now.

For IBL's functionality, we can refer to https://review.coreboot.org/c/coreboot/+/81314/7/src/soc/intel/common/pch/Kc....

File src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h:

https://review.coreboot.org/c/coreboot/+/81315/comment/5c93ffa9_012215e2 :
PS6, Line 3: DEVICE_AZALIA_H
> there's an integrated HDA device?

It is forked codes from previous generation (EBG).