Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence

[Maulik V Vaghela (Code Review)]

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Sridhar Siricilla.
Hello build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/62272

to look at the new patch set (#6).

Change subject: soc/intel/adl: Send EOP early in the boot sequence
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soc/intel/adl: Send EOP early in the boot sequence

As part of boot time optimization, one of the culprit was CSE where
response to End Of Post (EOP) command used to take ~60ms. Earlier patch
was pushed to delay the EOP to reduce response time to ~5-7 ms. During
this stage overall platform boot time was ~1.15 seconds.

Once boot time was optimized to ~ 1 seconds, CSE EOP time again
increased to ~80 ms since coreboot used to send EOP at the time where
CSE was busy. This created some back and forth moving of sending EOP
command function within coreboot sequence.
Upon debugging using traces, it was found that coreboot used to send
EOP late where CSE was busy loading other IP payload, so it might take
more time to respond.

In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow where
FSP used to send EOP once silicon init is done and coreboot used to
rely on FSP to send this message.

Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time
reduces from ~60 ms to ~20 ms on Brya board.

Note that once SoC code sends EOP, coreboot common code won't send it
again since common code already has check in case EOP is sent earlier.

BUG=b:211085685
BRANCH=None
TEST=Tested on Brya system before and after the changes. Observed ~40ms
savings in boot time.

Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b
Signed-off-by: MAULIK V VAGHELA 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.c
2 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62272/6