Change in coreboot[master]: lenovo/g505s: fix the IRQs and create the good MP tables

[Mike Banon (Code Review)]

Attention is currently required from: Alexander Couzens, Patrick Rudolph.
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58750 )

Change subject: lenovo/g505s: fix the IRQs and create the good MP tables
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Patch Set 1:

(3 comments)

Patchset:

PS1: 
Helpful comments by Arthur Heymans that are still on TODO list:

"All this ACPI, hardware config, mptable and pirqtable synchronisation is just messy. With Intel we solved this by generating most at runtime: see southbridge/intel/common/acpi_pirq_data.c . That solution is quite general and could easily be ported to AMD."

Today I tried using the results obtained by this cycle (see below) - that's what the "dynamic generation" would've given me - and have updated all the IRQ tables & routing accordingly. However, despite my best efforts, a laptop is running super slow (plagued by bad IRQs?) and doesn't detect SATA at all.

ACPI_PIRQ_GEN: PCI: 00:00.0: int_pin=0 int_pin-pirq_a=0
ACPI_PIRQ_GEN: PCI: 00:00.2: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:01.0: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:01.1: int_pin=2 int_pin-pirq_a=2
ACPI_PIRQ_GEN: PCI: 00:02.0: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:04.0: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:05.0: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:11.0: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:12.0: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:12.2: int_pin=2 int_pin-pirq_a=2
ACPI_PIRQ_GEN: PCI: 00:13.0: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:13.2: int_pin=2 int_pin-pirq_a=2
ACPI_PIRQ_GEN: PCI: 00:14.0: int_pin=0 int_pin-pirq_a=0
ACPI_PIRQ_GEN: PCI: 00:14.2: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:14.3: int_pin=0 int_pin-pirq_a=0
ACPI_PIRQ_GEN: PCI: 00:14.4: int_pin=0 int_pin-pirq_a=0
ACPI_PIRQ_GEN: PCI: 00:14.5: int_pin=3 int_pin-pirq_a=3
ACPI_PIRQ_GEN: PCI: 00:16.0: int_pin=1 int_pin-pirq_a=1
ACPI_PIRQ_GEN: PCI: 00:16.2: int_pin=2 int_pin-pirq_a=2
ACPI_PIRQ_GEN: PCI: 00:18.0: int_pin=0 int_pin-pirq_a=0
ACPI_PIRQ_GEN: PCI: 00:18.1: int_pin=0 int_pin-pirq_a=0
ACPI_PIRQ_GEN: PCI: 00:18.2: int_pin=0 int_pin-pirq_a=0
ACPI_PIRQ_GEN: PCI: 00:18.3: int_pin=0 int_pin-pirq_a=0
ACPI_PIRQ_GEN: PCI: 00:18.4: int_pin=0 int_pin-pirq_a=0
ACPI_PIRQ_GEN: PCI: 00:18.5: int_pin=0 int_pin-pirq_a=0

"What you want to is get the INT pin from PCI config and look that up in the 0xC00 IO config space. (This is sort of the equivalent of what Intel has in RCBA, see southbridge/intel/common/rcba_pirq.c)"

P.S. Is it possible to merge this static routing, if it's always working and better than the old routing?

File src/mainboard/lenovo/g505s/mptable.c:

https://review.coreboot.org/c/coreboot/+/58750/comment/4f9e2aa6_0b1166a3 
PS1, Line 180: PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_C]);
1) You can just loop over the discovered PCI devices, find out which INT they are using and look that up in mainboard_intr_data[].

2) Ack, will try using this code from ./src/southbridge/intel/common/acpi_pirq_gen.c:
...
pci_dev = PCI_SLOT(dev->path.pci.devfn);
int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);
...

https://review.coreboot.org/c/coreboot/+/58750/comment/1e3cad0c_3a4a8863 
PS1, Line 183: 0x1
This is dynamically allocated so you want to look at ->link_list->secondary of the PCIe devices.