Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38634 )
Change subject: util/msrtool: Fix typos ......................................................................
util/msrtool: Fix typos
The Intel docs also call it "Scalable Bus Speed", so the typo is on us.
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f util/msrtool/*.c
Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610 Signed-off-by: Patrick Georgi pgeorgi@google.com --- M util/msrtool/intel_atom.c M util/msrtool/intel_core2_later.c M util/msrtool/intel_nehalem.c 3 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/38634/1
diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index 489e0a0..3dc2bd6 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -39,7 +39,7 @@ {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { { BITS_EOT } }}, {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { @@ -148,7 +148,7 @@ /* if CPUID.01H: ECX[15] = 1 */ {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 50, RESERVED }, diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 95e8e91..287e241 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -125,8 +125,8 @@ { 0, 1, RESERVED }, { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { - /* This field indicates the intended scaleable bus clock speed */ + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + /* This field indicates the intended scalable bus clock speed */ { 63, 61, RESERVED }, { 2, 3, "Speed", "R/O", PRESENT_BIN, { { MSR1(0), "267 MHz (FSB 1067)" }, @@ -790,7 +790,7 @@ }}, {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 56, RESERVED }, diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 726ad0a..d3cb142 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -42,8 +42,8 @@ { BITS_EOT } }}, /* FIXME: This MSR not documented for Nehalem */ - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { - /* This field indicates the intended scaleable bus clock speed */ + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + /* This field indicates the intended scalable bus clock speed */ { BITS_EOT } }}, {0xce, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PLATFORM_INFO", "", { @@ -1329,7 +1329,7 @@ /* if CPUID.01H: ECX[15] = 1 */ {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 50, RESERVED },
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38634 )
Change subject: util/msrtool: Fix typos ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38634/1/util/msrtool/intel_atom.c File util/msrtool/intel_atom.c:
https://review.coreboot.org/c/coreboot/+/38634/1/util/msrtool/intel_atom.c@4... PS1, Line 42: {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/38634/1/util/msrtool/intel_core2_la... File util/msrtool/intel_core2_later.c:
https://review.coreboot.org/c/coreboot/+/38634/1/util/msrtool/intel_core2_la... PS1, Line 128: {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/38634/1/util/msrtool/intel_nehalem.... File util/msrtool/intel_nehalem.c:
https://review.coreboot.org/c/coreboot/+/38634/1/util/msrtool/intel_nehalem.... PS1, Line 45: {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { space required after that ',' (ctx:VxV)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38634 )
Change subject: util/msrtool: Fix typos ......................................................................
Patch Set 1: Code-Review+1
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38634 )
Change subject: util/msrtool: Fix typos ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38634 )
Change subject: util/msrtool: Fix typos ......................................................................
util/msrtool: Fix typos
The Intel docs also call it "Scalable Bus Speed", so the typo is on us.
Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f util/msrtool/*.c
Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610 Signed-off-by: Patrick Georgi pgeorgi@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38634 Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M util/msrtool/intel_atom.c M util/msrtool/intel_core2_later.c M util/msrtool/intel_nehalem.c 3 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve HAOUAS Elyes: Looks good to me, approved
diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index 489e0a0..3dc2bd6 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -39,7 +39,7 @@ {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { { BITS_EOT } }}, {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { @@ -148,7 +148,7 @@ /* if CPUID.01H: ECX[15] = 1 */ {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 50, RESERVED }, diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 95e8e91..287e241 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -125,8 +125,8 @@ { 0, 1, RESERVED }, { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { - /* This field indicates the intended scaleable bus clock speed */ + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + /* This field indicates the intended scalable bus clock speed */ { 63, 61, RESERVED }, { 2, 3, "Speed", "R/O", PRESENT_BIN, { { MSR1(0), "267 MHz (FSB 1067)" }, @@ -790,7 +790,7 @@ }}, {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 56, RESERVED }, diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 726ad0a..d3cb142 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -42,8 +42,8 @@ { BITS_EOT } }}, /* FIXME: This MSR not documented for Nehalem */ - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { - /* This field indicates the intended scaleable bus clock speed */ + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + /* This field indicates the intended scalable bus clock speed */ { BITS_EOT } }}, {0xce, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PLATFORM_INFO", "", { @@ -1329,7 +1329,7 @@ /* if CPUID.01H: ECX[15] = 1 */ {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 50, RESERVED },
-
build bot (Jenkins) (Code Review) -
HAOUAS Elyes (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)