Change in coreboot[master]: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update
V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47557 )
Change subject: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update ......................................................................
mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update
This patch modifies flash layout to add ME_RW_A/B to add the CSE RW blob and also enable the CSE RW update feature for JSLRVP
BUG=b:169077783 TEST= Built for jslrvp. Verified that CSE RW and metadata files are included in cbfs.
Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d Signed-off-by: V Sowmya v.sowmya@intel.com --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 2 files changed, 7 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47557/1
diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 1125a9b..01b9ab7 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -21,6 +21,7 @@ select SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_RW_UPDATE
config MAINBOARD_DIR string diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 05f4592..57be7f1 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -7,13 +7,15 @@ SI_BIOS@0x600000 0xA00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x12ffc0 + RW_FWID_A@0x13ffc0 0x40 + ME_RW_A(CBFS)@0x140000 0x190000 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x12ffc0 + RW_FWID_B@0x13ffc0 0x40 + ME_RW_B(CBFS)@0x140000 0x190000 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 {
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47557 )
Change subject: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47557/1/src/mainboard/intel/jasperl... File src/mainboard/intel/jasperlake_rvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/47557/1/src/mainboard/intel/jasperl... PS1, Line 24: SOC_INTEL_CSE_RW_UPDATE All the update related configs will have to be in one place - either here or in config.${BOARD} in chromium tree. They can't be split into two different places.
Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D, Balaji Manigandan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47557
to look at the new patch set (#2).
Change subject: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update ......................................................................
mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update
This patch modifies flash layout to add ME_RW_A/B to add the CSE RW blob and also enable the CSE RW update feature for JSLRVP
BUG=b:169077783 TEST= Built for jslrvp. Verified that CSE RW and metadata files are included in cbfs.
Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d Signed-off-by: V Sowmya v.sowmya@intel.com --- M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 1 file changed, 6 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47557/2
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47557 )
Change subject: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47557/1/src/mainboard/intel/jasperl... File src/mainboard/intel/jasperlake_rvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/47557/1/src/mainboard/intel/jasperl... PS1, Line 24: SOC_INTEL_CSE_RW_UPDATE
All the update related configs will have to be in one place - either here or in config. […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47557 )
Change subject: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update ......................................................................
Patch Set 4: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47557 )
Change subject: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update ......................................................................
Patch Set 4: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47557 )
Change subject: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update ......................................................................
mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update
This patch modifies flash layout to add ME_RW_A/B to add the CSE RW blob and also enable the CSE RW update feature for JSLRVP
BUG=b:169077783 TEST= Built for jslrvp. Verified that CSE RW and metadata files are included in cbfs.
Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d Signed-off-by: V Sowmya v.sowmya@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47557 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 1 file changed, 6 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 05f4592..57be7f1 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -7,13 +7,15 @@ SI_BIOS@0x600000 0xA00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x12ffc0 + RW_FWID_A@0x13ffc0 0x40 + ME_RW_A(CBFS)@0x140000 0x190000 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x12ffc0 + RW_FWID_B@0x13ffc0 0x40 + ME_RW_B(CBFS)@0x140000 0x190000 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 {
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Furquan Shaikh (Code Review) -
Karthik Ramasubramanian (Code Review)
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V Sowmya (Code Review)