Change in coreboot[master]: docs: intel fsp: add memory retraining bug on SPS systems

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36935 )

Change subject: docs: intel fsp: add memory retraining bug on SPS systems
......................................................................

docs: intel fsp: add memory retraining bug on SPS systems

FSP2.0 forces MRC retraining on cold boot on Intel SPS systems.

Change-Id: I3ce812309b46bdb580557916a775043fda63667f
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Georgi 
---
M Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
M Documentation/soc/intel/fsp/index.md
2 files changed, 7 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved

diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
index adee88a..2cb945a 100644
--- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
@@ -31,7 +31,7 @@
 These issues apply to all boards. Have a look at the board-specific issues, too.

- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726)
-- MRC caching does not work with cold boot
+- MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0])

## ToDo

diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
index aac7b35..769b98b 100644
--- a/Documentation/soc/intel/fsp/index.md
+++ b/Documentation/soc/intel/fsp/index.md
@@ -34,6 +34,11 @@
   * Workaround: none
   * Issue on public tracker: [Issue 22]

+* MRC forces memory re-training on cold boot on boards with Intel SPS
+  * Releases 3.7.1, 3.7.6
+  * Workaround: Flash Intel ME instead of SPS
+  * Issue on public tracker: [Issue 41]
+
 ### BraswellFsp
 * Internal UART can't be disabled using PcdEnableHsuart*
   * Release MR2
@@ -66,4 +71,5 @@
 [Issue 15]: https://github.com/IntelFsp/FSP/issues/15
 [Issue 22]: https://github.com/IntelFsp/FSP/issues/22
 [Issue 35]: https://github.com/IntelFsp/FSP/issues/35
+[Issue 41]: https://github.com/IntelFsp/FSP/issues/41