Change in coreboot[4.11_branch]: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48461 )
Change subject: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide ......................................................................
src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide
Change-Id: I6c2c25ce6dc82b8f5bf9d41eb5cecd3b3274d032 Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/quadcore/quadcore_id.c M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/southbridge/amd/sr5650/cmn.h 5 files changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/48461/1
diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index a1dc1f4..08cca13 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -65,7 +65,7 @@ if (is_fam15h()) { enable_cc6 = 0;
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18)) enable_cc6 = 1; #else diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index 7ec1bdb..ccc8c44 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -42,7 +42,7 @@ uint32_t family; uint32_t model;
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); #else f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); @@ -109,7 +109,7 @@ uint32_t f5x84; uint8_t core_count;
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84); #else f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84); diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 23e9232..8975641 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -21,7 +21,7 @@ #include "raminit.h" #include <northbridge/amd/amdmct/amddefs.h>
-#if !ENV_PCI_SIMPLE_DEVICE +#if !__SIMPLE_DEVICE__ u32 Get_NB32(u32 dev, u32 reg) { return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 52032e9..8cb8c58 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -69,7 +69,7 @@ return s3nv_region.region.offset; }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static uint32_t read_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t reg) #else @@ -79,7 +79,7 @@ { if (is_fam15h()) { uint32_t dword; -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -98,7 +98,7 @@ return pci_read_config32(dev, reg); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static void write_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t reg, uint32_t value) #else @@ -108,7 +108,7 @@ { if (is_fam15h()) { uint32_t dword; -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -127,7 +127,7 @@ pci_write_config32(dev, reg, value); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static uint32_t read_amd_dct_index_register(pci_devfn_t dev, uint32_t index_ctl_reg, uint32_t index) #else @@ -147,7 +147,7 @@ return dword; }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static uint32_t read_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t index_ctl_reg, uint32_t index) #else @@ -158,7 +158,7 @@ { if (is_fam15h()) { uint32_t dword; -#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index 9588105..ef66a5d 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -34,7 +34,7 @@ #define AB_INDX 0xCD8 #define AB_DATA (AB_INDX+4)
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) #else static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) @@ -44,7 +44,7 @@ return pci_read_config32(dev, index_reg + 0x4); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) #else @@ -56,7 +56,7 @@ pci_write_config32(dev, index_reg + 0x4, data); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index) @@ -65,7 +65,7 @@ return nb_read_index((nb_dev), NBMISC_INDEX, (index)); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void nbmisc_write_index(struct device *nb_dev, u32 index, @@ -75,7 +75,7 @@ nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -92,7 +92,7 @@ } }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 htiu_read_index(struct device *nb_dev, u32 index) @@ -101,7 +101,7 @@ return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data) @@ -110,7 +110,7 @@ nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 nbmc_read_index(struct device *nb_dev, u32 index) @@ -119,7 +119,7 @@ return nb_read_index((nb_dev), NBMC_INDEX, (index)); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) @@ -128,7 +128,7 @@ nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -145,7 +145,7 @@ } }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -162,7 +162,7 @@ } }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask, u8 val) #else @@ -179,7 +179,7 @@ } }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -196,7 +196,7 @@ } }
-#if ENV_PCI_SIMPLE_DEVICE +#if __SIMPLE_DEVICE__ static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask, u32 val) #else
Michał Żygowski has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/48461 )
Change subject: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide ......................................................................
src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide
TEST=timeless build does not change the SHA256 hash of KGPE-D16 rom
Change-Id: I6c2c25ce6dc82b8f5bf9d41eb5cecd3b3274d032 Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/quadcore/quadcore_id.c M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/southbridge/amd/sr5650/cmn.h 5 files changed, 25 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/48461/2
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48461 )
Change subject: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48461/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48461/2//COMMIT_MSG@7 PS2, Line 7: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide Please explain the WHY in the commit messages.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48461 )
Change subject: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide ......................................................................
Patch Set 2:
Reverts CB:35654 so what's the motivation for the change?
I'm guessing some of the followup changes of removing .c includes breaks without this, did you check for missing <device/pci_ops.h> includes?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48461 )
Change subject: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide ......................................................................
Patch Set 2:
Patch Set 2:
Reverts CB:35654 so what's the motivation for the change?
I'm guessing some of the followup changes of removing .c includes breaks without this, did you check for missing <device/pci_ops.h> includes?
Every change is at least build tested, so missing includes shouldn't bean issue here.
My motivation is that ENV_PCI_SIMPLE_DEVICE is an internal symbol in pci_ops.h, so it shouldn't be used anywhere in the source. The appropriate symbol is __SIMPLE_DEVICE__ (as I understand it) which is used treewide.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48461 )
Change subject: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Reverts CB:35654 so what's the motivation for the change?
I'm guessing some of the followup changes of removing .c includes breaks without this, did you check for missing <device/pci_ops.h> includes?
Every change is at least build tested, so missing includes shouldn't bean issue here.
My motivation is that ENV_PCI_SIMPLE_DEVICE is an internal symbol in pci_ops.h, so it shouldn't be used anywhere in the source. The appropriate symbol is __SIMPLE_DEVICE__ (as I understand it) which is used treewide.
You can discuss this in CB:35652
It's __SIMPLE_DEVICE__ that should disappear instead. The change is analogous to removals of using __BOOTBLOCK__, __ROMSTAGE__, __ROMCC__ etc.
Michał Żygowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48461 )
Change subject: src: Replace ENV_PCI_SIMPLE_DEVICE with __SIMPLE_DEVICE__ treewide ......................................................................
Abandoned
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)
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Stefan Reinauer (Code Review)