[S] Change in coreboot[master]: mb/google/sarien: Implement touchscreen power sequencing

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74237 )

Change subject: mb/google/sarien: Implement touchscreen power sequencing
......................................................................

mb/google/sarien: Implement touchscreen power sequencing

For touchscreens on sarien, drive the enable GPIO high starting in
romstage while holding in reset, then disable the reset GPIO in
ramstage. This will allow coreboot to detect the presence of i2c
touchscreens during ACPI SSDT generation (implemented in a subsequent
commit).

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I3ce7bfc0fa4c03c0bb96bebaa3c3d256f886ecc4
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74237
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
---
M src/mainboard/google/sarien/variants/arcada/gpio.c
M src/mainboard/google/sarien/variants/sarien/gpio.c
2 files changed, 38 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
index 63df675..45aed5f 100644
--- a/src/mainboard/google/sarien/variants/arcada/gpio.c
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -242,6 +242,12 @@
 /* M2_SKT2_CFG0 */	PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
 };

+static const struct pad_config romstage_gpio_table[] = {
+	/* Enable touchscreen, hold in reset */
+	PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
+	PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TOUCH_SCREEN_PD# */
+};
+
 const struct pad_config *variant_gpio_table(size_t *num)
 {
    *num = ARRAY_SIZE(gpio_table);
@@ -256,8 +262,8 @@

const struct pad_config *variant_romstage_gpio_table(size_t *num)
 {
-	*num = 0;
-	return NULL;
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
 }

static const struct cros_gpio cros_gpios[] = {
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index f9797d3..5eb5607 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -230,6 +230,12 @@
 /* M2_SKT2_CFG0 */	PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
 };

+static const struct pad_config romstage_gpio_table[] = {
+	/* Enable touchscreen, hold in reset */
+	PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
+	PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TOUCH_SCREEN_PD# */
+};
+
 const struct pad_config *variant_gpio_table(size_t *num)
 {
    *num = ARRAY_SIZE(gpio_table);
@@ -244,8 +250,8 @@

const struct pad_config *variant_romstage_gpio_table(size_t *num)
 {
-	*num = 0;
-	return NULL;
+	*num = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
 }

static const struct cros_gpio cros_gpios[] = {