Change in coreboot[master]: soc/mediatek/mt8192: disable_l2c_sram in ramstage

[Yidi Lin (Code Review)]

Hello CK HU,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/46387

to review the following change.

Change subject: soc/mediatek/mt8192: disable_l2c_sram in ramstage
......................................................................

soc/mediatek/mt8192: disable_l2c_sram in ramstage

Signed-off-by: CK Hu 
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/mmu_operations.c
M src/soc/mediatek/mt8192/soc.c
3 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46387/1

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 8bc7b74..891d38a 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -33,6 +33,7 @@
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-y += emi.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += soc.c
 ramstage-y += ../common/timer.c
diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c
new file mode 100644
index 0000000..fb3620e
--- /dev/null
+++ b/src/soc/mediatek/mt8192/mmu_operations.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/mcucfg.h>
+#include <soc/mmu_operations.h>
+
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
+
+void mtk_soc_disable_l2c_sram(void)
+{
+	unsigned long v;
+
+	SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
+	dsb();
+
+	__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+	v |= (0xf << 4);
+	__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+	dsb();
+
+	do {
+		__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+	} while (((v >> 0x4) & 0xf) != 0xf);
+
+	SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
+	dsb();
+}
diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c
index 9850fa6..6978406 100644
--- a/src/soc/mediatek/mt8192/soc.c
+++ b/src/soc/mediatek/mt8192/soc.c
@@ -2,6 +2,7 @@

#include <device/device.h>
 #include <soc/emi.h>
+#include <soc/mmu_operations.h>
 #include <symbols.h>

static void soc_read_resources(struct device *dev)
@@ -11,6 +12,7 @@

static void soc_init(struct device *dev)
 {
+	mtk_mmu_disable_l2c_sram();
 }

static struct device_operations soc_ops = {

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46387 )

Change subject: soc/mediatek/mt8192: disable_l2c_sram in ramstage
......................................................................

Patch Set 3: Code-Review+2

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46387 )

Change subject: soc/mediatek/mt8192: disable_l2c_sram in ramstage
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46387/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46387/4//COMMIT_MSG@8 
PS4, Line 8: 
Why?

Change in coreboot[master]: soc/mediatek/mt8192: Turn off L2C SRAM and return it to L2 cache

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, CK HU,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46387

to look at the new patch set (#5).

Change subject: soc/mediatek/mt8192: Turn off L2C SRAM and return it to L2 cache
......................................................................

soc/mediatek/mt8192: Turn off L2C SRAM and return it to L2 cache

Mediatek SoC uses part of L2 cache as SRAM before DRAM ready.
After DRAM ready, disable_l2c_sram is called to return SRAM to L2 cache.

Signed-off-by: CK Hu 
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/mmu_operations.c
M src/soc/mediatek/mt8192/soc.c
3 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46387/5

Change in coreboot[master]: soc/mediatek/mt8192: Turn off L2C SRAM and return it to L2 cache

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46387 )

Change subject: soc/mediatek/mt8192: Turn off L2C SRAM and return it to L2 cache
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46387/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46387/4//COMMIT_MSG@8 
PS4, Line 8:
> Why?

please refer to the commit message of patchset 5.

Change in coreboot[master]: soc/mediatek/mt8192: Turn off L2C SRAM and return it to L2 cache

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46387 )

Change subject: soc/mediatek/mt8192: Turn off L2C SRAM and return it to L2 cache
......................................................................

Patch Set 6:

(5 comments)

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@7 
PS6, Line 7: return it to
reconfigure as

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@9 
PS6, Line 9: of 
of the

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@9 
PS6, Line 9: DRAM ready
DRAM is ready

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@10 
PS6, Line 10: DRAM ready
DRAM is ready

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@10 
PS6, Line 10: disable_l2c_sram is called to return SRAM to L2 cache
we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache.

Change in coreboot[master]: soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache

[Yidi Lin (Code Review)]

Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, CK HU,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46387

to look at the new patch set (#7).

Change subject: soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache
......................................................................

soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache

Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.

Signed-off-by: CK Hu 
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/mmu_operations.c
M src/soc/mediatek/mt8192/soc.c
3 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46387/7

Change in coreboot[master]: soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46387 )

Change subject: soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache
......................................................................

Patch Set 7:

(5 comments)

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@7 
PS6, Line 7: return it to
> reconfigure as

Ack

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@9 
PS6, Line 9: of
> of the

Ack

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@9 
PS6, Line 9: DRAM ready
> DRAM is ready

Ack

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@10 
PS6, Line 10: disable_l2c_sram is called to return SRAM to L2 cache
> we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache.

Ack

https://review.coreboot.org/c/coreboot/+/46387/6//COMMIT_MSG@10 
PS6, Line 10: DRAM ready
> DRAM is ready

Ack

Change in coreboot[master]: soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46387 )

Change subject: soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache
......................................................................

Patch Set 7: Code-Review+2

Change in coreboot[master]: soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46387 )

Change subject: soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache
......................................................................

soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache

Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.

Signed-off-by: CK Hu 
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387
Reviewed-by: Hung-Te Lin 
Tested-by: build bot (Jenkins) 
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/mmu_operations.c
M src/soc/mediatek/mt8192/soc.c
3 files changed, 33 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index fb3b11d..8b2831c 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -30,6 +30,7 @@
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-y += emi.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += soc.c
 ramstage-y += ../common/timer.c
diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c
new file mode 100644
index 0000000..fb3620e
--- /dev/null
+++ b/src/soc/mediatek/mt8192/mmu_operations.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/mcucfg.h>
+#include <soc/mmu_operations.h>
+
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
+
+void mtk_soc_disable_l2c_sram(void)
+{
+	unsigned long v;
+
+	SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
+	dsb();
+
+	__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+	v |= (0xf << 4);
+	__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+	dsb();
+
+	do {
+		__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+	} while (((v >> 0x4) & 0xf) != 0xf);
+
+	SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
+	dsb();
+}
diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c
index 9850fa6..6978406 100644
--- a/src/soc/mediatek/mt8192/soc.c
+++ b/src/soc/mediatek/mt8192/soc.c
@@ -2,6 +2,7 @@

#include <device/device.h>
 #include <soc/emi.h>
+#include <soc/mmu_operations.h>
 #include <symbols.h>

static void soc_read_resources(struct device *dev)
@@ -11,6 +12,7 @@

static void soc_init(struct device *dev)
 {
+	mtk_mmu_disable_l2c_sram();
 }

static struct device_operations soc_ops = {