[S] Change in coreboot[master]: soc/intel/alderlake: Disable PCIe clock gating

[Patrick Rudolph (Code Review)]

Attention is currently required from: Angel Pons, Subrata Banik, Tarun Tuli.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76687?usp=email )

Change subject: soc/intel/alderlake: Disable PCIe clock gating
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Patch Set 3:

(1 comment)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/76687/comment/f7baed26_0f5ede91 :
PS1, Line 923: #if CONFIG(FSP_TYPE_IOT)
> Huh, not fully awake yet... So, Client FSP doesn't have these UPDs yet? If so, this can be resolved.

That's correct. Once Intel releases a new Client FSP it will have the same UPDs and the preprocessor guard can be removed. It doesn't have them *yet*.