Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage

[Jianjun Wang (Code Review)]

Attention is currently required from: Shelley Chen, Paul Menzel, Yu-Ping Wu.
Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Paul Menzel, Yu-Ping Wu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/62359

to look at the new patch set (#2).

Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage
......................................................................

soc/mediatek: PCI: Assert PERST# at bootblock stage

Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be
delayed 100ms (TPVPERL) for the power and clock to become stable.

Assert PERST# at bootblock stage to reduce the impact of the 100ms
delay.

TEST=Build pass and boot up to kernel successfully via SSD on Cherry
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x1987
    PCI SSVID : 0x1987
    SN        : 28F40713077B0012602
    MN        : Phison ESE1A043-X28
    RAB       : 0x1
    AERL      : 0x3
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model Phison ESE1A043-X28

BUG=b:178565024

Signed-off-by: Jianjun Wang 
Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d
---
M src/soc/mediatek/mt8195/Makefile.inc
M src/soc/mediatek/mt8195/bootblock.c
2 files changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/62359/2