[L] Change in coreboot[main]: mainboard: Drop redundant PciRpEnable from devicetrees

[Nico Huber (Code Review)]

Attention is currently required from: Angel Pons, Christian Walter, Erik van den Bogaert, Frans Hendriks, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nicholas Sudsgaard, Nick Vaccaro, Patrick Rudolph, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford, Werner Zeh.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79935?usp=email )

Change subject: mainboard: Drop redundant PciRpEnable from devicetrees
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Patch Set 3:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/79935/comment/f72791e0_2cd6097a :
PS3, Line 13: as I do not know the PCIe addresses of some of the enabled root ports.
Thanks for taking on the work! I believe I already did all the RVPs
(had to do some boards for local compilation tests). I made one patch
per soc/ dir, though. And you based this on the first, so only skylake
changes will work here.

Feel free to amend my commits, or let me know if I should incorporate
yours. In the meantime, I'll try to rebase your patch on my chain so we
can see how well things compile :)