Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33228
Change subject: [NOTFORMERGE]3rdparty/blobs: Update submodulue ......................................................................
[NOTFORMERGE]3rdparty/blobs: Update submodulue
The sandybridge DACHE_RAM_BASE is relocated and allows for more flexible location of the stack.
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33228/1
diff --git a/3rdparty/blobs b/3rdparty/blobs index ca6cfcd..62c370c 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 +Subproject commit 62c370c76a4dae72dffbb452e2b30bd911967290
Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: [NOTFORMERGE]3rdparty/blobs: Update submodulue ......................................................................
[NOTFORMERGE]3rdparty/blobs: Update submodulue
The sandybridge DACHE_RAM_BASE is relocated and allows for more flexible location of the stack.
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M 3rdparty/blobs M src/northbridge/intel/sandybridge/Kconfig 2 files changed, 4 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33228/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33228
to look at the new patch set (#3).
Change subject: [NOTFORMERGE_YET]3rdparty/blobs: Update submodulue, SNB improvements ......................................................................
[NOTFORMERGE_YET]3rdparty/blobs: Update submodulue, SNB improvements
The sandybridge DACHE_RAM_BASE is relocated and allows for more flexible location of the stack.
The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack wrt the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired)
This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB.
This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region.
TODO: update when blobs repo master is updated.
TESTED on T520 (boots and resumes from S3 with mrc.bin).
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M 3rdparty/blobs M src/arch/x86/car.ld M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_mrc.c 4 files changed, 30 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33228/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: [NOTFORMERGE_YET]3rdparty/blobs: Update submodulue, SNB improvements ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/33228/3/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/#/c/33228/3/src/northbridge/intel/sandybridge/ra... PS3, Line 287: + DCACHE_RAM_MRC_VAR_SIZE code indent should use tabs where possible
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: [NOTFORMERGE_YET]3rdparty/blobs: Update submodulue, SNB improvements ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/33228/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33228/3//COMMIT_MSG@7 PS3, Line 7: submodulue submoule
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: [NOTFORMERGE_YET]3rdparty/blobs: Update submodulue, SNB improvements ......................................................................
Patch Set 3: Code-Review+1
Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33228
to look at the new patch set (#4).
Change subject: 3rdparty/blobs: Update submodulue, SNB improvements ......................................................................
3rdparty/blobs: Update submodulue, SNB improvements
The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack wrt the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired)
This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB.
This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region.
TESTED on T520 (boots and resumes from S3 with mrc.bin).
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M 3rdparty/blobs M src/arch/x86/car.ld M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_mrc.c 4 files changed, 30 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33228/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: 3rdparty/blobs: Update submodulue, SNB improvements ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/33228/4/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/#/c/33228/4/src/northbridge/intel/sandybridge/ra... PS4, Line 287: + DCACHE_RAM_MRC_VAR_SIZE code indent should use tabs where possible
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: 3rdparty/blobs: Update submodulue, SNB improvements ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/33228/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33228/4//COMMIT_MSG@19 PS4, Line 19: CONFIG_DACHE_RAM_MRC_VAR_SIZE rename it?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: 3rdparty/blobs: Update submodulue, SNB improvements ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/#/c/33228/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33228/4//COMMIT_MSG@7 PS4, Line 7: submodulue submodule
https://review.coreboot.org/#/c/33228/4//COMMIT_MSG@10 PS4, Line 10: wrt (Nit) I'd use 'w.r.t.' for clarity.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: 3rdparty/blobs: Update submodulue, SNB improvements ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/33228/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33228/4//COMMIT_MSG@19 PS4, Line 19: CONFIG_DACHE_RAM_MRC_VAR_SIZE
rename it?
It's somewhat in line with the semantics of other users of that symbol, with "size of CAR region blob uses".
Hello Angel Pons, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33228
to look at the new patch set (#5).
Change subject: 3rdparty/blobs: Update submodule, SNB improvements ......................................................................
3rdparty/blobs: Update submodule, SNB improvements
The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack w.r.t. the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired)
This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB.
This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region.
TESTED on T520 (boots and resumes from S3 with mrc.bin).
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M 3rdparty/blobs M src/arch/x86/car.ld M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_mrc.c 4 files changed, 30 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33228/5
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: 3rdparty/blobs: Update submodule, SNB improvements ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/33228/5/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/#/c/33228/5/src/northbridge/intel/sandybridge/ra... PS5, Line 273: | COREBOOT STACK | Not strictly just the stack but also .bss.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: 3rdparty/blobs: Update submodule, SNB improvements ......................................................................
Patch Set 5: Code-Review+2
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33228 )
Change subject: 3rdparty/blobs: Update submodule, SNB improvements ......................................................................
3rdparty/blobs: Update submodule, SNB improvements
The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack w.r.t. the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired)
This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB.
This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region.
TESTED on T520 (boots and resumes from S3 with mrc.bin).
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M 3rdparty/blobs M src/arch/x86/car.ld M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_mrc.c 4 files changed, 30 insertions(+), 18 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/3rdparty/blobs b/3rdparty/blobs index ca6cfcd..d7600dd 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit ca6cfcdbe1cdeb38c2622ee2e5236cc4657e3377 +Subproject commit d7600dd8718a076f0f9a89e53968b484254624dc diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 29b3600..5802b02 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -91,13 +91,6 @@ _car_global_end = .; _car_relocatable_data_end = .;
-#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && !CONFIG(USE_NATIVE_RAMINIT) - . = ABSOLUTE(0xff7e1000); - _mrc_pool = .; - . += 0x5000; - _emrc_pool = .; -#endif - #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) _car_stack_start = .; _car_stack_end = _car_region_end; diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 4f9da00..59cf92c 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -78,12 +78,13 @@ help The MRC blob requires it to be at 0xf0000000.
-if USE_NATIVE_RAMINIT - config DCACHE_RAM_BASE hex default 0xfefe0000
+ +if USE_NATIVE_RAMINIT + config DCACHE_RAM_SIZE hex default 0x20000 @@ -96,17 +97,13 @@
if !USE_NATIVE_RAMINIT
-config DCACHE_RAM_BASE - hex - default 0xff7e0000 - config DCACHE_RAM_SIZE hex - default 0x1c000 + default 0x17000
config DCACHE_RAM_MRC_VAR_SIZE hex - default 0x4000 + default 0x9000
config MRC_FILE string "Intel System Agent path and filename" diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index e88d356..a8acfbf 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -265,9 +265,31 @@ report_memory_config(); }
-/* These are the location and structure of MRC_VAR data in CAR. */ +/* These are the location and structure of MRC_VAR data in CAR. + The CAR region looks like this: + +------------------+ -> DCACHE_RAM_BASE + | | + | | + | COREBOOT STACK | + | | + | | + +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE + | | + | MRC HEAP | + | size = 0x5000 | + | | + +------------------+ + | | + | MRC VAR | + | size = 0x4000 | + | | + +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE + + DCACHE_RAM_MRC_VAR_SIZE + + */ #define DCACHE_RAM_MRC_VAR_BASE \ - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + \ + CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000)
struct mrc_var_data { u32 acpi_timer_flag;
-
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