Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Hello build bot (Jenkins), Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63293

to look at the new patch set (#2).

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
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soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

The patch adds mechanism in the Alder Lake SoC code to control PCH
USB2 Phy power gating from devicetree.

BUG=b:221461379
TEST=Build and boot Gimble board

Signed-off-by: Sridhar Siricilla 
Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63293/2