EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32242
Change subject: mb/google/sarien: resvered gpio pins for D3 cold control ......................................................................
mb/google/sarien: resvered gpio pins for D3 cold control
Base on HW change, resvered gpio pins for D3 cold control. A13,A15 for Card reader H13 for M.2 SSD
BUG=b:123263562 TEST=N/A
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32242/1
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index ff311b1..91934b1 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -31,9 +31,9 @@ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* BM_BUSY# */ PAD_NC(GPP_A12, NONE), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* Card reader D3 cold */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 1, DEEP), /* Card reader D3 cold */ /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_NC(GPP_A18, NONE), @@ -198,7 +198,7 @@ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), -/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),
Hello Lijian Zhao, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32242
to look at the new patch set (#2).
Change subject: mb/google/sarien: resvered gpio pins for D3 cold control ......................................................................
mb/google/sarien: resvered gpio pins for D3 cold control
Base on HW change, resvered gpio pins for D3 cold control. A13,A15 for Card reader H13 for M.2 SSD
BUG=b:123263562 TEST=N/A
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32242/2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32242 )
Change subject: mb/google/sarien: resvered gpio pins for D3 cold control ......................................................................
Patch Set 2:
This is final decision for next build.Please help review it.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32242 )
Change subject: mb/google/sarien: resvered gpio pins for D3 cold control ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG@7 PS2, Line 7: resvered Reserve
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG@9 PS2, Line 9: Base Based
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG@9 PS2, Line 9: resvered reserve
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG@9 PS2, Line 9: HW change What revision?
https://review.coreboot.org/#/c/32242/2/src/mainboard/google/sarien/variants... File src/mainboard/google/sarien/variants/sarien/gpio.c:
https://review.coreboot.org/#/c/32242/2/src/mainboard/google/sarien/variants... PS2, Line 200: */ Please add a space before */.
Hello Lijian Zhao, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32242
to look at the new patch set (#3).
Change subject: mb/google/sarien: resvere gpio pins for D3 cold control ......................................................................
mb/google/sarien: resvere gpio pins for D3 cold control
Based on HW change, resvere gpio pins for D3 cold control. A13,A15 for Card reader H13 for M.2 SSD
BUG=b:123263562 TEST=N/A
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32242/3
Hello Lijian Zhao, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32242
to look at the new patch set (#4).
Change subject: mb/google/sarien: Resvere gpio pins for D3 cold control ......................................................................
mb/google/sarien: Resvere gpio pins for D3 cold control
Based on HW change, resvere gpio pins for D3 cold control. A13,A15 for Card reader H13 for M.2 SSD
BUG=b:123263562 TEST=N/A
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32242/4
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32242 )
Change subject: mb/google/sarien: Resvere gpio pins for D3 cold control ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG@7 PS2, Line 7: resvered
Reserve
Done
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG@9 PS2, Line 9: resvered
reserve
Done
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG@9 PS2, Line 9: HW change
What revision?
Google asked ODM can't share any hw revision on public.
https://review.coreboot.org/#/c/32242/2//COMMIT_MSG@9 PS2, Line 9: Base
Based
Done
Hello Lijian Zhao, Duncan Laurie, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32242
to look at the new patch set (#5).
Change subject: mb/google/sarien: Reserve gpio pins for D3 cold control ......................................................................
mb/google/sarien: Reserve gpio pins for D3 cold control
Based on HW change, reserve gpio pins for D3 cold control. A13,A15 for Card reader H13 for M.2 SSD
BUG=b:123263562 TEST=N/A
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32242/5
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32242 )
Change subject: mb/google/sarien: Reserve gpio pins for D3 cold control ......................................................................
Patch Set 5:
my terrible spelling...
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32242 )
Change subject: mb/google/sarien: Reserve gpio pins for D3 cold control ......................................................................
Patch Set 5:
(1 comment)
Mark another mistake.
https://review.coreboot.org/#/c/32242/5/src/mainboard/google/sarien/variants... File src/mainboard/google/sarien/variants/sarien/gpio.c:
https://review.coreboot.org/#/c/32242/5/src/mainboard/google/sarien/variants... PS5, Line 200: GPP_H13 oops should be H12.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32242 )
Change subject: mb/google/sarien: Reserve gpio pins for D3 cold control ......................................................................
Patch Set 6:
(2 comments)
All mistakes are fixed. Please help review it, thx.
https://review.coreboot.org/#/c/32242/2/src/mainboard/google/sarien/variants... File src/mainboard/google/sarien/variants/sarien/gpio.c:
https://review.coreboot.org/#/c/32242/2/src/mainboard/google/sarien/variants... PS2, Line 200: */
Please add a space before */.
Done
https://review.coreboot.org/#/c/32242/5/src/mainboard/google/sarien/variants... File src/mainboard/google/sarien/variants/sarien/gpio.c:
https://review.coreboot.org/#/c/32242/5/src/mainboard/google/sarien/variants... PS5, Line 200: GPP_H13
oops should be H12.
Done
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32242 )
Change subject: mb/google/sarien: Reserve gpio pins for D3 cold control ......................................................................
Patch Set 6: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32242 )
Change subject: mb/google/sarien: Reserve gpio pins for D3 cold control ......................................................................
mb/google/sarien: Reserve gpio pins for D3 cold control
Based on HW change, reserve gpio pins for D3 cold control. A13,A15 for Card reader H13 for M.2 SSD
BUG=b:123263562 TEST=N/A
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32242 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index ff311b1..19fd45c 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -31,9 +31,9 @@ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* BM_BUSY# */ PAD_NC(GPP_A12, NONE), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_NC(GPP_A18, NONE), @@ -197,8 +197,8 @@ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), -/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), -/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* /D3 cold RST */ +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),