Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48543 )
Change subject: soc/intel/elkhartlake: Update IRQ routing settings ......................................................................
soc/intel/elkhartlake: Update IRQ routing settings
Update IRQ routing settings.
Extra reference: - ACPI spec 6.2.13 _PRT
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 --- M src/soc/intel/elkhartlake/acpi/pci_irqs.asl M src/soc/intel/elkhartlake/include/soc/irq.h 2 files changed, 145 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48543/1
diff --git a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl index aa494a7..8f511f2 100644 --- a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl +++ b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl @@ -3,99 +3,161 @@ #include <soc/irq.h>
Name (PICP, Package () { - Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - - Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 }, - - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - - Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 }, - - Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - - Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ }, + //D31 + Package () { 0x001FFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001FFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001FFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001FFFFF, 3, 0, PCH_IRQ_D }, + //D30 + Package () { 0x001EFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001EFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001EFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001EFFFF, 3, 0, PCH_IRQ_D }, + //D29 + Package () { 0x001DFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001DFFFF, 1, 0, PCH_IRQ34 }, + Package () { 0x001DFFFF, 2, 0, PCH_IRQ35 }, + Package () { 0x001DFFFF, 3, 0, PCH_IRQ36 }, + //D28 + Package () { 0x001CFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001CFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001CFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001CFFFF, 3, 0, PCH_IRQ_D }, + //D27 + Package () { 0x001BFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001BFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001BFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001BFFFF, 3, 0, PCH_IRQ_D }, + //D26 + Package () { 0x001AFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001AFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001AFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001AFFFF, 3, 0, PCH_IRQ_D }, + //D25 + Package () { 0x0019FFFF, 0, 0, PCH_IRQ31 }, + Package () { 0x0019FFFF, 1, 0, PCH_IRQ32 }, + Package () { 0x0019FFFF, 2, 0, PCH_IRQ33 }, + //D24 + Package () { 0x0018FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0018FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0018FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0018FFFF, 3, 0, PCH_IRQ_D }, + //D23 + Package () { 0x0017FFFF, 0, 0, PCH_IRQ_A }, + //D22 + Package () { 0x0016FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0016FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0016FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0016FFFF, 3, 0, PCH_IRQ_D }, + //D21 + Package () { 0x0015FFFF, 0, 0, PCH_IRQ27 }, + Package () { 0x0015FFFF, 1, 0, PCH_IRQ28 }, + Package () { 0x0015FFFF, 2, 0, PCH_IRQ29 }, + Package () { 0x0015FFFF, 3, 0, PCH_IRQ30 }, + //D20 + Package () { 0x0014FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0014FFFF, 1, 0, PCH_IRQ_B }, + //D19 + Package () { 0x0013FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0013FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0013FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0013FFFF, 3, 0, PCH_IRQ_D }, + //D18 + Package () { 0x0012FFFF, 0, 0, PCH_IRQ24 }, + Package () { 0x0012FFFF, 1, 0, PCH_IRQ25 }, + Package () { 0x0012FFFF, 2, 0, PCH_IRQ26 }, + //D17 + Package () { 0x0011FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0011FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0011FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0011FFFF, 3, 0, PCH_IRQ_D }, + //D16 + Package () { 0x0010FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0010FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0010FFFF, 2, 0, PCH_IRQ_C }, /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0008FFFF, 0, 0, PCH_IRQ_A }, /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0004FFFF, 0, 0, PCH_IRQ_A }, /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0002FFFF, 0, 0, PCH_IRQ_A }, })
Name (PICN, Package () { + //D31 Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 }, - + //D30 Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 }, - + //D29 + Package () { 0x001DFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001DFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001DFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001DFFFF, 3, 0, PCH_IRQ11 }, + //D28 Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 }, - + //D27 + Package () { 0x001BFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001BFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001BFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001BFFFF, 3, 0, PCH_IRQ11 }, + //D26 Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 }, - + Package () { 0x001AFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001AFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001AFFFF, 3, 0, PCH_IRQ11 }, + //D25 Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 }, - + //D24 + Package () { 0x0018FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0018FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0018FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0018FFFF, 3, 0, PCH_IRQ11 }, + //D23 Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 }, - + //D22 Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 }, Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 }, - + //D21 Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 }, Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 }, - + //D20 Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 }, - Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 }, - Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 }, - + //D19 + Package () { 0x0013FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0013FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0013FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0013FFFF, 3, 0, PCH_IRQ11 }, + //D18 + Package () { 0x0012FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0012FFFF, 2, 0, PCH_IRQ11 }, + //D17 + Package () { 0x0011FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0011FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0011FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0011FFFF, 3, 0, PCH_IRQ11 }, + //D16 + Package () { 0x0010FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0010FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0010FFFF, 2, 0, PCH_IRQ11 }, /* SA GNA Device */ Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 }, /* SA Thermal Device */ Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 }, /* SA IGFX Device */ diff --git a/src/soc/intel/elkhartlake/include/soc/irq.h b/src/soc/intel/elkhartlake/include/soc/irq.h index ac45424..432b7ae 100644 --- a/src/soc/intel/elkhartlake/include/soc/irq.h +++ b/src/soc/intel/elkhartlake/include/soc/irq.h @@ -8,29 +8,33 @@
#define PCH_IRQ10 10 #define PCH_IRQ11 11 - -/* LPSS Device IRQs */ -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 +#define PCH_IRQ24 24 +#define PCH_IRQ25 25 +#define PCH_IRQ26 26 +#define PCH_IRQ27 27 +#define PCH_IRQ28 28 +#define PCH_IRQ29 29 +#define PCH_IRQ30 30 +#define PCH_IRQ31 31 +#define PCH_IRQ32 32 +#define PCH_IRQ33 33 +#define PCH_IRQ34 34 +#define PCH_IRQ35 35 +#define PCH_IRQ36 36
/* PCI shared IRQs */ -#define PCH_IRQ_16 16 -#define PCH_IRQ_17 17 -#define PCH_IRQ_18 18 -#define PCH_IRQ_19 19 -#define PCH_IRQ_20 20 -#define PCH_IRQ_21 21 -#define PCH_IRQ_22 22 -#define PCH_IRQ_23 23 +#define PCH_IRQ_A 16 +#define PCH_IRQ_B 17 +#define PCH_IRQ_C 18 +#define PCH_IRQ_D 19 +#define PCH_IRQ_E 20 +#define PCH_IRQ_F 21 +#define PCH_IRQ_G 22 +#define PCH_IRQ_H 23 + +/* LPSS Device IRQs */ +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 +#define LPSS_UART2_IRQ 33
#endif /* _EHL_IRQ_H_ */
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48543 )
Change subject: soc/intel/elkhartlake: Update IRQ routing settings ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48543/2/src/soc/intel/elkhartlake/a... File src/soc/intel/elkhartlake/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/48543/2/src/soc/intel/elkhartlake/a... PS2, Line 6: // Please use one common comment style for a single line comment /* D31 */ or /* Device 31 */
This is valid for a lot following comments. Where possible, could you please use a more describing comment like "PCIe root ports" or the like for device 28?
Hello Felix Singer, build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48543
to look at the new patch set (#3).
Change subject: soc/intel/elkhartlake: Update IRQ routing settings ......................................................................
soc/intel/elkhartlake: Update IRQ routing settings
Update IRQ routing settings.
Extra reference: - ACPI spec 6.2.13 _PRT
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 --- M src/soc/intel/elkhartlake/acpi/pci_irqs.asl M src/soc/intel/elkhartlake/include/soc/irq.h 2 files changed, 145 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48543/3
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48543 )
Change subject: soc/intel/elkhartlake: Update IRQ routing settings ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48543/2/src/soc/intel/elkhartlake/a... File src/soc/intel/elkhartlake/acpi/pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/48543/2/src/soc/intel/elkhartlake/a... PS2, Line 6: //
Please use one common comment style for a single line comment […]
Done
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48543 )
Change subject: soc/intel/elkhartlake: Update IRQ routing settings ......................................................................
Patch Set 3: Code-Review+2
Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48543 )
Change subject: soc/intel/elkhartlake: Update IRQ routing settings ......................................................................
soc/intel/elkhartlake: Update IRQ routing settings
Update IRQ routing settings.
Extra reference: - ACPI spec 6.2.13 _PRT
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48543 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/soc/intel/elkhartlake/acpi/pci_irqs.asl M src/soc/intel/elkhartlake/include/soc/irq.h 2 files changed, 145 insertions(+), 79 deletions(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl index aa494a7..d73f031 100644 --- a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl +++ b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl @@ -3,99 +3,161 @@ #include <soc/irq.h>
Name (PICP, Package () { - Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - - Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 }, - - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - - Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 }, - - Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - - Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ }, + /* D31 */ + Package () { 0x001FFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001FFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001FFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001FFFFF, 3, 0, PCH_IRQ_D }, + /* D30 */ + Package () { 0x001EFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001EFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001EFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001EFFFF, 3, 0, PCH_IRQ_D }, + /* Intel PSE Devices */ + Package () { 0x001DFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001DFFFF, 1, 0, PCH_IRQ34 }, + Package () { 0x001DFFFF, 2, 0, PCH_IRQ35 }, + Package () { 0x001DFFFF, 3, 0, PCH_IRQ36 }, + /* PCIe Root Ports */ + Package () { 0x001CFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001CFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001CFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001CFFFF, 3, 0, PCH_IRQ_D }, + /* Intel PSE I2C Devices */ + Package () { 0x001BFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001BFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001BFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001BFFFF, 3, 0, PCH_IRQ_D }, + /* D26 */ + Package () { 0x001AFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001AFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001AFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001AFFFF, 3, 0, PCH_IRQ_D }, + /* D25 */ + Package () { 0x0019FFFF, 0, 0, PCH_IRQ31 }, + Package () { 0x0019FFFF, 1, 0, PCH_IRQ32 }, + Package () { 0x0019FFFF, 2, 0, PCH_IRQ33 }, + /* Intel PSE Devices */ + Package () { 0x0018FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0018FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0018FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0018FFFF, 3, 0, PCH_IRQ_D }, + /* SATA */ + Package () { 0x0017FFFF, 0, 0, PCH_IRQ_A }, + /* ME Interfaces */ + Package () { 0x0016FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0016FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0016FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0016FFFF, 3, 0, PCH_IRQ_D }, + /* I2C Devices */ + Package () { 0x0015FFFF, 0, 0, PCH_IRQ27 }, + Package () { 0x0015FFFF, 1, 0, PCH_IRQ28 }, + Package () { 0x0015FFFF, 2, 0, PCH_IRQ29 }, + Package () { 0x0015FFFF, 3, 0, PCH_IRQ30 }, + /* USB Devices */ + Package () { 0x0014FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0014FFFF, 1, 0, PCH_IRQ_B }, + /* Intel PSE Devices */ + Package () { 0x0013FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0013FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0013FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0013FFFF, 3, 0, PCH_IRQ_D }, + /* D18 */ + Package () { 0x0012FFFF, 0, 0, PCH_IRQ24 }, + Package () { 0x0012FFFF, 1, 0, PCH_IRQ25 }, + Package () { 0x0012FFFF, 2, 0, PCH_IRQ26 }, + /* Intel PSE Devices */ + Package () { 0x0011FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0011FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0011FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0011FFFF, 3, 0, PCH_IRQ_D }, + /* D16 */ + Package () { 0x0010FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0010FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0010FFFF, 2, 0, PCH_IRQ_C }, /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0008FFFF, 0, 0, PCH_IRQ_A }, /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0004FFFF, 0, 0, PCH_IRQ_A }, /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0002FFFF, 0, 0, PCH_IRQ_A }, })
Name (PICN, Package () { + /* D31 */ Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 }, - + /* D30 */ Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 }, - + /* Intel PSE Devices */ + Package () { 0x001DFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001DFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001DFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001DFFFF, 3, 0, PCH_IRQ11 }, + /* PCIe Root Ports */ Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 }, - + /* Intel PSE I2C Devices */ + Package () { 0x001BFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001BFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001BFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001BFFFF, 3, 0, PCH_IRQ11 }, + /* D26 */ Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 }, - + Package () { 0x001AFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001AFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001AFFFF, 3, 0, PCH_IRQ11 }, + /* D25 */ Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 }, - + /* Intel PSE Devices */ + Package () { 0x0018FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0018FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0018FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0018FFFF, 3, 0, PCH_IRQ11 }, + /* SATA */ Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 }, - + /* ME Interfaces */ Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 }, Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 }, - + /* I2C Devices */ Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 }, Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 }, - + /* USB Devices */ Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 }, - Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 }, - Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 }, - + /* Intel PSE Devices */ + Package () { 0x0013FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0013FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0013FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0013FFFF, 3, 0, PCH_IRQ11 }, + /* D18 */ + Package () { 0x0012FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0012FFFF, 2, 0, PCH_IRQ11 }, + /* Intel PSE Devices */ + Package () { 0x0011FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0011FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0011FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0011FFFF, 3, 0, PCH_IRQ11 }, + /* D16 */ + Package () { 0x0010FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0010FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0010FFFF, 2, 0, PCH_IRQ11 }, /* SA GNA Device */ Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 }, /* SA Thermal Device */ Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 }, /* SA IGFX Device */ diff --git a/src/soc/intel/elkhartlake/include/soc/irq.h b/src/soc/intel/elkhartlake/include/soc/irq.h index ac45424..432b7ae 100644 --- a/src/soc/intel/elkhartlake/include/soc/irq.h +++ b/src/soc/intel/elkhartlake/include/soc/irq.h @@ -8,29 +8,33 @@
#define PCH_IRQ10 10 #define PCH_IRQ11 11 - -/* LPSS Device IRQs */ -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 +#define PCH_IRQ24 24 +#define PCH_IRQ25 25 +#define PCH_IRQ26 26 +#define PCH_IRQ27 27 +#define PCH_IRQ28 28 +#define PCH_IRQ29 29 +#define PCH_IRQ30 30 +#define PCH_IRQ31 31 +#define PCH_IRQ32 32 +#define PCH_IRQ33 33 +#define PCH_IRQ34 34 +#define PCH_IRQ35 35 +#define PCH_IRQ36 36
/* PCI shared IRQs */ -#define PCH_IRQ_16 16 -#define PCH_IRQ_17 17 -#define PCH_IRQ_18 18 -#define PCH_IRQ_19 19 -#define PCH_IRQ_20 20 -#define PCH_IRQ_21 21 -#define PCH_IRQ_22 22 -#define PCH_IRQ_23 23 +#define PCH_IRQ_A 16 +#define PCH_IRQ_B 17 +#define PCH_IRQ_C 18 +#define PCH_IRQ_D 19 +#define PCH_IRQ_E 20 +#define PCH_IRQ_F 21 +#define PCH_IRQ_G 22 +#define PCH_IRQ_H 23 + +/* LPSS Device IRQs */ +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 +#define LPSS_UART2_IRQ 33
#endif /* _EHL_IRQ_H_ */