Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48258 )
Change subject: soc/intel/common/dmi: Add support for locking down SRL ......................................................................
soc/intel/common/dmi: Add support for locking down SRL
This change adds support to lock down the DMI configuration in dmi_lockdown_cfg() by setting Secure Register Lock (SRL) bit in DMI control register.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f --- M src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/lockdown/lockdown.c 2 files changed, 10 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48258/1
diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h index 55bf20d..8b12602 100644 --- a/src/soc/intel/common/block/include/intelblocks/dmi.h +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -8,6 +8,9 @@ #define PCR_DMI_DMICTL 0x2234 #define PCR_DMI_DMICTL_SRLOCK (1 << 31)
+#define PCR_DMI_GCS 0x274C +#define PCR_DMI_GCS_BILD (1 << 0) + /* * Takes base, size and destination ID and configures the GPMR * for accessing the region. diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index b10306e..d9495a4 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -2,6 +2,7 @@
#include <bootstate.h> #include <intelblocks/cfg.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelpch/lockdown.h> @@ -9,9 +10,6 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h>
-#define PCR_DMI_GCS 0x274C -#define PCR_DMI_GCS_BILD (1 << 0) - /* * This function will get lockdown config specific to soc. * @@ -40,6 +38,12 @@ * "1b": LPC/eSPI */ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); + + /* + * Set Secure Register Lock (SRL) bit in DMI control register to lock + * DMI configuration. + */ + pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK); }
static void fast_spi_lockdown_cfg(int chipset_lockdown)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48258 )
Change subject: soc/intel/common/dmi: Add support for locking down SRL ......................................................................
Patch Set 1: Code-Review+2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48258 )
Change subject: soc/intel/common/dmi: Add support for locking down SRL ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48258 )
Change subject: soc/intel/common/dmi: Add support for locking down SRL ......................................................................
soc/intel/common/dmi: Add support for locking down SRL
This change adds support to lock down the DMI configuration in dmi_lockdown_cfg() by setting Secure Register Lock (SRL) bit in DMI control register.
BUG=b:171534504
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I98a82ce4a2f73f8a1504e5ddf77ff2e81ae3f53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48258 Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/include/intelblocks/dmi.h M src/soc/intel/common/pch/lockdown/lockdown.c 2 files changed, 10 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h index 55bf20d..8b12602 100644 --- a/src/soc/intel/common/block/include/intelblocks/dmi.h +++ b/src/soc/intel/common/block/include/intelblocks/dmi.h @@ -8,6 +8,9 @@ #define PCR_DMI_DMICTL 0x2234 #define PCR_DMI_DMICTL_SRLOCK (1 << 31)
+#define PCR_DMI_GCS 0x274C +#define PCR_DMI_GCS_BILD (1 << 0) + /* * Takes base, size and destination ID and configures the GPMR * for accessing the region. diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index b10306e..d9495a4 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -2,6 +2,7 @@
#include <bootstate.h> #include <intelblocks/cfg.h> +#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelpch/lockdown.h> @@ -9,9 +10,6 @@ #include <soc/pcr_ids.h> #include <soc/soc_chip.h>
-#define PCR_DMI_GCS 0x274C -#define PCR_DMI_GCS_BILD (1 << 0) - /* * This function will get lockdown config specific to soc. * @@ -40,6 +38,12 @@ * "1b": LPC/eSPI */ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); + + /* + * Set Secure Register Lock (SRL) bit in DMI control register to lock + * DMI configuration. + */ + pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK); }
static void fast_spi_lockdown_cfg(int chipset_lockdown)
-
Duncan Laurie (Code Review) -
Furquan Shaikh (Code Review)
-
Srinidhi N Kaushik (Code Review)