Change in coreboot[master]: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63550 )

Change subject: soc/intel/fast_spi.c: Use smarter mtrr code in ramstage
......................................................................

soc/intel/fast_spi.c: Use smarter mtrr code in ramstage

mtrr_use_temp_range is a lot smarter than the plain set_var_mtrr. It
will compute a new optimal solution with the temp ranges included
while also taking care of the cleanup before loading the payload/s3
resume.

Change-Id: I283ba07fc12c410be39dfdc828657598237247c1
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/63550/1

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 5a76df3..20463d3 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -199,6 +199,11 @@

static void fast_spi_enable_cache_range(unsigned int base, unsigned int size)
 {
+	if (ENV_RAMSTAGE) {
+		mtrr_use_temp_range(base, size, MTRR_TYPE_WRPROT);
+		return;
+	}
+
    const int type = MTRR_TYPE_WRPROT;
    int mtrr = get_free_var_mtrr();
    if (mtrr == -1) {