Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39113 )
Change subject: soc/intel/tigerlake: Add Jasper Lake GPIO definitions ......................................................................
soc/intel/tigerlake: Add Jasper Lake GPIO definitions
Define GPIO communities and groups for Jasper Lake. Since there are some difference between Tiger Lake and Jasper Lake, rename the existing GPIO definitions as Tiger Lake specific.
BUG=None TEST=Build the volteer and dedede mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I2ee2601f5761354c3ae24d0fb13f902d0d49496f --- M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi/gpio.asl A src/soc/intel/tigerlake/acpi/gpio_jsl.asl A src/soc/intel/tigerlake/acpi/gpio_tgl.asl A src/soc/intel/tigerlake/gpio_jsl.c R src/soc/intel/tigerlake/gpio_tgl.c M src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h 12 files changed, 1,969 insertions(+), 866 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39113/1
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 56119f5..e17d637 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -20,11 +20,13 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c -bootblock-y += gpio.c +bootblock-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +bootblock-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c bootblock-y += p2sb.c
romstage-y += espi.c -romstage-y += gpio.c +romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c romstage-y += reset.c
@@ -36,7 +38,8 @@ ramstage-y += finalize.c ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c -ramstage-y += gpio.c +ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c @@ -46,7 +49,8 @@ ramstage-y += systemagent.c ramstage-y += sd.c
-smm-y += gpio.c +smm-$(CONFIG_SOC_INTEL_JASPERLAKE) += gpio_jsl.c +smm-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c smm-y += p2sb.c smm-y += pmc.c smm-y += pmutil.c diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index f6cccfb..63d3b4c 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -12,202 +12,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <soc/gpio_defs.h> -#include <soc/irq.h> -#include <soc/pcr_ids.h>
-Device (GCM0) -{ - Name (_HID, "INT34C5") - Name (_UID, 0) - Name (_DDN, "GPIO Controller Community 0") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} - -Device (GCM1) -{ - Name (_HID, "INT34C5") - Name (_UID, 1) - Name (_DDN, "GPIO Controller Community 1") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} - -Device (GCM4) -{ - Name (_HID, "INT34C5") - Name (_UID, 4) - Name (_DDN, "GPIO Controller Community 4") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} - -Device (GCM5) -{ - Name (_HID, "INT34C5") - Name (_UID, 5) - Name (_DDN, "GPIO Controller Community 5") - - Name (RBUF, ResourceTemplate() - { - Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - Return (^RBUF) - } - Method (_STA) - { - Return (0xF) - } -} - -/* - * Get GPIO DW0 Address - * Arg0 - GPIO Number - */ -Method (GADD, 1, NotSerialized) -{ - /* GPIO Community 0 */ - If (Arg0 >= GPP_B0 && Arg0 <= GPP_A24) - { - Local0 = PID_GPIOCOM0 - Local1 = Arg0 - GPP_B0 - } - /* GPIO Community 1 */ - If (Arg0 >= GPP_S0 && Arg0 <= vI2S2_RXD) - { - Local0 = PID_GPIOCOM1 - Local1 = Arg0 - GPP_S0 - } - /* GPIO Community 2 */ - If (Arg0 >= GPD0 && Arg0 <= GPD_DRAM_RESETB) - { - Local0 = PID_GPIOCOM2 - Local1 = Arg0 - GPD0 - } - /* GPIO Community 4 */ - If (Arg0 >= GPP_C0 && Arg0 <= GPP_DBG_PMODE) - { - Local0 = PID_GPIOCOM4 - Local1 = Arg0 - GPP_C0 - } - /* GPIO Community 5 */ - If (Arg0 >= GPP_R0 && Arg0 <= GPP_CLK_LOOPBK) - { - Local0 = PID_GPIOCOM5 - Local1 = Arg0 - GPP_R0 - } - Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) - Return (Local2) -} - -/* - * Get GPIO Value - * Arg0 - GPIO Number - */ -Method (GRXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT) - - Return (Local0) -} - -/* - * Get GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (GTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - Local0 = GPIOTXSTATE_MASK & VAL0 - - Return (Local0) -} - -/* - * Set GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (STXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - VAL0 |= GPIOTXSTATE_MASK -} - -/* - * Clear GPIO Tx Value - * Arg0 - GPIO Number - */ -Method (CTXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - VAL0 &= ~GPIOTXSTATE_MASK -} +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "gpio_tgl.asl" +#else + #include "gpio_jsl.asl" +#endif diff --git a/src/soc/intel/tigerlake/acpi/gpio_jsl.asl b/src/soc/intel/tigerlake/acpi/gpio_jsl.asl new file mode 100644 index 0000000..5c82ff9 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/gpio_jsl.asl @@ -0,0 +1,213 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/gpio_defs.h> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Device (GCM0) +{ + Name (_HID, "INT34C8") + Name (_UID, 0) + Name (_DDN, "GPIO Controller Community 0") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +Device (GCM1) +{ + Name (_HID, "INT34C8") + Name (_UID, 1) + Name (_DDN, "GPIO Controller Community 1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +Device (GCM4) +{ + Name (_HID, "INT34C8") + Name (_UID, 4) + Name (_DDN, "GPIO Controller Community 4") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +Device (GCM5) +{ + Name (_HID, "INT34C8") + Name (_UID, 5) + Name (_DDN, "GPIO Controller Community 5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPP_F0 && Arg0 <= GPP_R7) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_F0 + } + /* GPIO Community 1 */ + If (Arg0 >= GPP_H0 && Arg0 <= GPP_C23) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_H0 + } + /* GPIO Community 2 */ + If (Arg0 >= GPD0 && Arg0 <= GPIO_DRAM_RESETB) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPD0 + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_L_BKLTEN && Arg0 <= GPIO_VGPIO_LNK_DN_3) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_L_BKLTEN + } + /* GPIO Community 5 */ + If (Arg0 >= GPP_G0 && Arg0 <= GPP_G7) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPP_G0 + } + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Get GPIO Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT) + + Return (Local0) +} + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = GPIOTXSTATE_MASK & VAL0 + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 |= GPIOTXSTATE_MASK +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 &= ~GPIOTXSTATE_MASK +} diff --git a/src/soc/intel/tigerlake/acpi/gpio_tgl.asl b/src/soc/intel/tigerlake/acpi/gpio_tgl.asl new file mode 100644 index 0000000..f6cccfb --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/gpio_tgl.asl @@ -0,0 +1,213 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/gpio_defs.h> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Device (GCM0) +{ + Name (_HID, "INT34C5") + Name (_UID, 0) + Name (_DDN, "GPIO Controller Community 0") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +Device (GCM1) +{ + Name (_HID, "INT34C5") + Name (_UID, 1) + Name (_DDN, "GPIO Controller Community 1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +Device (GCM4) +{ + Name (_HID, "INT34C5") + Name (_UID, 4) + Name (_DDN, "GPIO Controller Community 4") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +Device (GCM5) +{ + Name (_HID, "INT34C5") + Name (_UID, 5) + Name (_DDN, "GPIO Controller Community 5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + Return (^RBUF) + } + Method (_STA) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPP_B0 && Arg0 <= GPP_A24) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPP_B0 + } + /* GPIO Community 1 */ + If (Arg0 >= GPP_S0 && Arg0 <= vI2S2_RXD) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPP_S0 + } + /* GPIO Community 2 */ + If (Arg0 >= GPD0 && Arg0 <= GPD_DRAM_RESETB) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPD0 + } + /* GPIO Community 4 */ + If (Arg0 >= GPP_C0 && Arg0 <= GPP_DBG_PMODE) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPP_C0 + } + /* GPIO Community 5 */ + If (Arg0 >= GPP_R0 && Arg0 <= GPP_CLK_LOOPBK) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPP_R0 + } + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Get GPIO Value + * Arg0 - GPIO Number + */ +Method (GRXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT) + + Return (Local0) +} + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = GPIOTXSTATE_MASK & VAL0 + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 |= GPIOTXSTATE_MASK +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + VAL0 &= ~GPIOTXSTATE_MASK +} diff --git a/src/soc/intel/tigerlake/gpio_jsl.c b/src/soc/intel/tigerlake/gpio_jsl.c new file mode 100644 index 0000000..1739e82 --- /dev/null +++ b/src/soc/intel/tigerlake/gpio_jsl.c @@ -0,0 +1,190 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <soc/pmc.h> + +/* + * This file is created based on Intel Jasper Lake Processor Datasheet + * Document number: 618876 + */ + +static const struct reset_mapping rst_map[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, +}; +static const struct reset_mapping rst_map_com2[] = { + { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, + { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 }, +}; + +static const struct pad_group jsl_community0_groups[] = { + INTEL_GPP(GPP_F0, GPP_F0, GPP_F19), /* GPP_F */ + INTEL_GPP(GPP_F0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */ + INTEL_GPP(GPP_F0, GPP_B0, GSPI1_CLK_LOOPBK), /* GPP_B */ + INTEL_GPP(GPP_F0, GPP_A0, ESPI_CLK_LOOPBK), /* GPP_A */ + INTEL_GPP(GPP_F0, GPP_S0, GPP_S7), /* GPP_S */ + INTEL_GPP(GPP_F0, GPP_R0, GPP_R7), /* GPP_R */ +}; + +static const struct pad_group jsl_community1_groups[] = { + INTEL_GPP(GPP_H0, GPP_H0, GPP_H23), /* GPP_H */ + INTEL_GPP(GPP_H0, GPP_D0, SPI1_CLK_LOOPBK), /* GPP_D */ + INTEL_GPP(GPP_H0, VGPIO_0, VGPIO_39), /* GPP_VGPIO */ + INTEL_GPP(GPP_H0, GPP_C0, GPP_C23), /* GPP_C */ +}; + +/* This community is not visible to the OS */ +static const struct pad_group jsl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPIO_DRAM_RESETB), /* GPD */ +}; + +static const struct pad_group jsl_community4_groups[] = { + INTEL_GPP(GPIO_L_BKLTEN, GPIO_L_BKLTEN, GPIO_VGPIO_LNK_DN_3), /* GPP_E */ +}; + +static const struct pad_group jsl_community5_groups[] = { + INTEL_GPP(GPP_G0, GPP_G0, GPP_G7), /* GPP_G */ +}; + +static const struct pad_community jsl_communities[] = { + [COMM_0] = { /* GPP F, SPI, B, A, S, R */ + .port = PID_GPIOCOM0, + .first_pad = GPP_F0, + .last_pad = GPP_R7, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_BTA", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community0_groups, + .num_groups = ARRAY_SIZE(jsl_community0_groups), + }, + [COMM_1] = { /* GPP H, D, VGPIO, C */ + .port = PID_GPIOCOM1, + .first_pad = GPP_H0, + .last_pad = GPP_C23, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SDHU", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community1_groups, + .num_groups = ARRAY_SIZE(jsl_community1_groups), + }, + [COMM_2] = { /* GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPD0, + .last_pad = GPIO_DRAM_RESETB, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map_com2, + .num_reset_vals = ARRAY_SIZE(rst_map_com2), + .groups = jsl_community2_groups, + .num_groups = ARRAY_SIZE(jsl_community2_groups), + }, + [COMM_4] = { /* GPP E */ + .port = PID_GPIOCOM4, + .first_pad = GPIO_L_BKLTEN, + .last_pad = GPIO_VGPIO_LNK_DN_3, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_FCE", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community4_groups, + .num_groups = ARRAY_SIZE(jsl_community4_groups), + }, + [COMM_5] = { /* GPP G */ + .port = PID_GPIOCOM5, + .first_pad = GPP_G0, + .last_pad = GPP_G7, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_CPU_VBPIO", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = jsl_community5_groups, + .num_groups = ARRAY_SIZE(jsl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(jsl_communities); + return jsl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_F, GPP_F }, + { PMC_GPP_B, GPP_B }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_H, GPP_H }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_C, GPP_C }, + { PMC_GPD, GPP_GPD }, + { PMC_GPP_E, GPP_E }, + /* TODO: Fix the next route. Requires splitting PMC */ + { PMC_GPP_U, GPP_G }, + }; + *num = ARRAY_SIZE(routes); + return routes; +} diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio_tgl.c similarity index 100% rename from src/soc/intel/tigerlake/gpio.c rename to src/soc/intel/tigerlake/gpio_tgl.c diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index 6a5a6e2..1cd5ca6 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -16,303 +16,10 @@ #ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_ #define _SOC_TIGERLAKE_GPIO_DEFS_H_
-#ifndef __ACPI__ -#include <stddef.h> -#endif -#include <soc/gpio_soc_defs.h> +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "gpio_defs_tgl.h" +#else + #include "gpio_defs_jsl.h" +#endif /* CONFIG_SOC_INTEL_TIGERLAKE */
-#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ - -#define NUM_GPIO_COMx_GPI_REGS(n) \ - (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) - -#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) -#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) -#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) -#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) -#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) - -#define NUM_GPI_STATUS_REGS \ - ((NUM_GPIO_COM0_GPI_REGS) +\ - (NUM_GPIO_COM1_GPI_REGS) +\ - (NUM_GPIO_COM2_GPI_REGS) +\ - (NUM_GPIO_COM4_GPI_REGS) +\ - (NUM_GPIO_COM5_GPI_REGS)) -/* - * IOxAPIC IRQs for the GPIOs - */ - -/* Group B */ -#define GPP_B0_IRQ 0x18 -#define GPP_B1_IRQ 0x19 -#define GPP_B2_IRQ 0x1A -#define GPP_B3_IRQ 0x1B -#define GPP_B4_IRQ 0x1C -#define GPP_B5_IRQ 0x1D -#define GPP_B6_IRQ 0x1E -#define GPP_B7_IRQ 0x1F -#define GPP_B8_IRQ 0x20 -#define GPP_B9_IRQ 0x21 -#define GPP_B10_IRQ 0x22 -#define GPP_B11_IRQ 0x23 -#define GPP_B12_IRQ 0x24 -#define GPP_B13_IRQ 0x25 -#define GPP_B14_IRQ 0x26 -#define GPP_B15_IRQ 0x27 -#define GPP_B16_IRQ 0x28 -#define GPP_B17_IRQ 0x29 -#define GPP_B18_IRQ 0x2A -#define GPP_B19_IRQ 0x2B -#define GPP_B20_IRQ 0x2C -#define GPP_B21_IRQ 0x2D -#define GPP_B22_IRQ 0x2E -#define GPP_B23_IRQ 0x2F - -/* Group T */ -#define GPP_T0_IRQ 0x30 -#define GPP_T1_IRQ 0x31 -#define GPP_T2_IRQ 0x32 -#define GPP_T3_IRQ 0x33 -#define GPP_T4_IRQ 0x34 -#define GPP_T5_IRQ 0x35 -#define GPP_T6_IRQ 0x36 -#define GPP_T7_IRQ 0x37 -#define GPP_T8_IRQ 0x38 -#define GPP_T9_IRQ 0x39 -#define GPP_T10_IRQ 0x3A -#define GPP_T11IRQ 0x3B -#define GPP_T12_IRQ 0x3C -#define GPP_T13_IRQ 0x3D -#define GPP_T14_IRQ 0x3E -#define GPP_T15_IRQ 0x3F - -/* Group A */ -#define GPP_A0_IRQ 0x40 -#define GPP_A1_IRQ 0x41 -#define GPP_A2_IRQ 0x42 -#define GPP_A3_IRQ 0x43 -#define GPP_A4_IRQ 0x44 -#define GPP_A5_IRQ 0x45 -#define GPP_A6_IRQ 0x46 -#define GPP_A7_IRQ 0x47 -#define GPP_A8_IRQ 0x48 -#define GPP_A9_IRQ 0x49 -#define GPP_A10_IRQ 0x4A -#define GPP_A11_IRQ 0x4B -#define GPP_A12_IRQ 0x4C -#define GPP_A13_IRQ 0x4D -#define GPP_A14_IRQ 0x4E -#define GPP_A15_IRQ 0x4F -#define GPP_A16_IRQ 0x50 -#define GPP_A17_IRQ 0x51 -#define GPP_A18_IRQ 0x52 -#define GPP_A19_IRQ 0x53 -#define GPP_A20_IRQ 0x54 -#define GPP_A21_IRQ 0x55 -#define GPP_A22_IRQ 0x56 -#define GPP_A23_IRQ 0x57 - -/* Group R */ -#define GPP_R0_IRQ 0x58 -#define GPP_R1_IRQ 0x59 -#define GPP_R2_IRQ 0x5A -#define GPP_R3_IRQ 0x5B -#define GPP_R4_IRQ 0x5C -#define GPP_R5_IRQ 0x5D -#define GPP_R6_IRQ 0x5E -#define GPP_R7_IRQ 0x5F - - -/* Group D */ -#define GPD0_IRQ 0x60 -#define GPD1_IRQ 0x61 -#define GPD2_IRQ 0x62 -#define GPD3_IRQ 0x63 -#define GPD4_IRQ 0x64 -#define GPD5_IRQ 0x65 -#define GPD6_IRQ 0x66 -#define GPD7_IRQ 0x67 -#define GPD8_IRQ 0x68 -#define GPD9_IRQ 0x69 -#define GPD10_IRQ 0x6A -#define GPD11_IRQ 0x6B - -/* Group S */ -#define GPP_S0_IRQ 0x6C -#define GPP_S1_IRQ 0x6D -#define GPP_S2_IRQ 0x6E -#define GPP_S3_IRQ 0x6F -#define GPP_S4_IRQ 0x70 -#define GPP_S5_IRQ 0x71 -#define GPP_S6_IRQ 0x72 -#define GPP_S7_IRQ 0x73 - -/* Group H */ -#define GPP_H0_IRQ 0x74 -#define GPP_H1_IRQ 0x75 -#define GPP_H2_IRQ 0x76 -#define GPP_H3_IRQ 0x77 -#define GPP_H4_IRQ 0x18 -#define GPP_H5_IRQ 0x19 -#define GPP_H6_IRQ 0x1A -#define GPP_H7_IRQ 0x1B -#define GPP_H8_IRQ 0x1C -#define GPP_H9_IRQ 0x1D -#define GPP_H10_IRQ 0x1E -#define GPP_H11_IRQ 0x1F -#define GPP_H12_IRQ 0x20 -#define GPP_H13_IRQ 0x21 -#define GPP_H14_IRQ 0x22 -#define GPP_H15_IRQ 0x23 -#define GPP_H16_IRQ 0x24 -#define GPP_H17_IRQ 0x25 -#define GPP_H18_IRQ 0x26 -#define GPP_H19_IRQ 0x27 -#define GPP_H20_IRQ 0x28 -#define GPP_H21_IRQ 0x29 -#define GPP_H22_IRQ 0x2A -#define GPP_H23_IRQ 0x2B - -/* Group D */ -#define GPP_D0_IRQ 0x2C -#define GPP_D1_IRQ 0x2D -#define GPP_D2_IRQ 0x2E -#define GPP_D3_IRQ 0x2F -#define GPP_D4_IRQ 0x30 -#define GPP_D5_IRQ 0x31 -#define GPP_D6_IRQ 0x32 -#define GPP_D7_IRQ 0x33 -#define GPP_D8_IRQ 0x34 -#define GPP_D9_IRQ 0x35 -#define GPP_D10_IRQ 0x36 -#define GPP_D11_IRQ 0x37 -#define GPP_D12_IRQ 0x38 -#define GPP_D13_IRQ 0x39 -#define GPP_D14_IRQ 0x3A -#define GPP_D15_IRQ 0x3B -#define GPP_D16_IRQ 0x3C -#define GPP_D17_IRQ 0x3D -#define GPP_D18_IRQ 0x3E -#define GPP_D19_IRQ 0x3F - - -/* Group U */ -#define GPP_U0_IRQ 0x40 -#define GPP_U1IRQ 0x41 -#define GPP_U2_IRQ 0x42 -#define GPP_U3_IRQ 0x43 -#define GPP_U4_IRQ 0x44 -#define GPP_U5_IRQ 0x45 -#define GPP_U6_IRQ 0x46 -#define GPP_U7_IRQ 0x47 -#define GPP_U8_IRQ 0x48 -#define GPP_U9_IRQ 0x49 -#define GPP_U10_IRQ 0x4A -#define GPP_U11_IRQ 0x4B -#define GPP_U12_IRQ 0x4C -#define GPP_U13_IRQ 0x4D -#define GPP_U14_IRQ 0x4E -#define GPP_U15_IRQ 0x4F -#define GPP_U16_IRQ 0x50 -#define GPP_U17_IRQ 0x51 -#define GPP_U18_IRQ 0x52 -#define GPP_U19_IRQ 0x53 - - -#define GPP_VGPIO4_IRQ 0x54 - -/* Group F */ -#define GPP_F0_IRQ 0x56 -#define GPP_F1_IRQ 0x57 -#define GPP_F2_IRQ 0x58 -#define GPP_F3_IRQ 0x59 -#define GPP_F4_IRQ 0x5A -#define GPP_F5_IRQ 0x5B -#define GPP_F6_IRQ 0x5C -#define GPP_F7_IRQ 0x5D -#define GPP_F8_IRQ 0x5E -#define GPP_F9_IRQ 0x5F -#define GPP_F10_IRQ 0x60 -#define GPP_F11_IRQ 0x61 -#define GPP_F12_IRQ 0x62 -#define GPP_F13_IRQ 0x63 -#define GPP_F14_IRQ 0x64 -#define GPP_F15_IRQ 0x65 -#define GPP_F16_IRQ 0x66 -#define GPP_F17_IRQ 0x67 -#define GPP_F18_IRQ 0x68 -#define GPP_F19_IRQ 0x69 -#define GPP_F20_IRQ 0x6A -#define GPP_F21_IRQ 0x6B -#define GPP_F22_IRQ 0x6C -#define GPP_F23_IRQ 0x6D - -/* Group C */ -#define GPP_C0_iIRQ 0x6E -#define GPP_C1_IRQ 0x6F -#define GPP_C2_IRQ 0x70 -#define GPP_C3_IRQ 0x71 -#define GPP_C4_IRQ 0x72 -#define GPP_C5_IRQ 0x73 -#define GPP_C6_IRQ 0x74 -#define GPP_C7_IRQ 0x75 -#define GPP_C8_IRQ 0x76 -#define GPP_C9_IRQ 0x77 -#define GPP_C10_IRQ 0x18 -#define GPP_C11_IRQ 0x19 -#define GPP_C12_IRQ 0x1A -#define GPP_C13_IRQ 0x1B -#define GPP_C14_IRQ 0x1C -#define GPP_C15_IRQ 0x1D -#define GPP_C16_IRQ 0x1E -#define GPP_C17_IRQ 0x1F -#define GPP_C18_IRQ 0x20 -#define GPP_C19_IRQ 0x21 -#define GPP_C20_IRQ 0x22 -#define GPP_C21_IRQ 0x23 -#define GPP_C22_IRQ 0x24 -#define GPP_C23_IRQ 0x25 - - - -/* Group E */ -#define GPP_E0_IRQ 0x26 -#define GPP_E1_IRQ 0x27 -#define GPP_E2_IRQ 0x28 -#define GPP_E3_IRQ 0x29 -#define GPP_E4_IRQ 0x30 -#define GPP_E5_IRQ 0x31 -#define GPP_E6_IRQ 0x32 -#define GPP_E7_IRQ 0x33 -#define GPP_E8_IRQ 0x34 -#define GPP_E9_IRQ 0x35 -#define GPP_E10_IRQ 0x36 -#define GPP_E11_IRQ 0x37 -#define GPP_E12_IRQ 0x38 -#define GPP_E13_IRQ 0x39 -#define GPP_E14_IRQ 0x3A -#define GPP_E15_IRQ 0x3B -#define GPP_E16_IRQ 0x3C -#define GPP_E17_IRQ 0x3D -#define GPP_E18_IRQ 0x3E -#define GPP_E19_IRQ 0x3F -#define GPP_E20_IRQ 0x40 -#define GPP_E21_IRQ 0x41 -#define GPP_E22_IRQ 0x42 -#define GPP_E23_IRQ 0x43 - -/* Register defines. */ -#define GPIO_MISCCFG 0x10 -#define GPE_DW_SHIFT 8 -#define GPE_DW_MASK 0xfff00 -#define HOSTSW_OWN_REG_0 0xb0 -#define GPI_INT_STS_0 0x100 -#define GPI_INT_EN_0 0x110 -#define GPI_SMI_STS_0 0x180 -#define GPI_SMI_EN_0 0x1A0 -#define PAD_CFG_BASE 0x700 - -#define GPIORXSTATE_MASK 0x1 -#define GPIORXSTATE_SHIFT 1 -#define GPIOTXSTATE_MASK 0x1 #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h new file mode 100644 index 0000000..a1fb30c --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h @@ -0,0 +1,279 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_DEFS_JSL_H_ +#define _SOC_TIGERLAKE_GPIO_DEFS_JSL_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group F */ +#define GPP_F0_IRQ 0x40 +#define GPP_F1_IRQ 0x41 +#define GPP_F2_IRQ 0x42 +#define GPP_F3_IRQ 0x43 +#define GPP_F4_IRQ 0x44 +#define GPP_F5_IRQ 0x45 +#define GPP_F6_IRQ 0x46 +#define GPP_F7_IRQ 0x47 +#define GPP_F8_IRQ 0x48 +#define GPP_F9_IRQ 0x49 +#define GPP_F10_IRQ 0x4a +#define GPP_F11_IRQ 0x4b +#define GPP_F12_IRQ 0x4c +#define GPP_F13_IRQ 0x4d +#define GPP_F14_IRQ 0x4e +#define GPP_F15_IRQ 0x4f +#define GPP_F16_IRQ 0x50 +#define GPP_F17_IRQ 0x51 +#define GPP_F18_IRQ 0x52 +#define GPP_F19_IRQ 0x53 + +/* Group B */ +#define GPP_B0_IRQ 0x20 +#define GPP_B1_IRQ 0x21 +#define GPP_B2_IRQ 0x22 +#define GPP_B3_IRQ 0x23 +#define GPP_B4_IRQ 0x24 +#define GPP_B5_IRQ 0x25 +#define GPP_B6_IRQ 0x26 +#define GPP_B7_IRQ 0x27 +#define GPP_B8_IRQ 0x28 +#define GPP_B9_IRQ 0x29 +#define GPP_B10_IRQ 0x2a +#define GPP_B11_IRQ 0x2b +#define GPP_B12_IRQ 0x2c +#define GPP_B13_IRQ 0x2d +#define GPP_B14_IRQ 0x2e +#define GPP_B15_IRQ 0x2f +#define GPP_B16_IRQ 0x30 +#define GPP_B17_IRQ 0x31 +#define GPP_B18_IRQ 0x32 +#define GPP_B19_IRQ 0x33 +#define GPP_B20_IRQ 0x34 +#define GPP_B21_IRQ 0x35 +#define GPP_B22_IRQ 0x36 +#define GPP_B23_IRQ 0x37 + +/* Group A */ +#define GPP_A0_IRQ 0x38 +#define GPP_A1_IRQ 0x39 +#define GPP_A2_IRQ 0x3a +#define GPP_A3_IRQ 0x3b +#define GPP_A4_IRQ 0x3c +#define GPP_A5_IRQ 0x3d +#define GPP_A6_IRQ 0x3e +#define GPP_A7_IRQ 0x3f +#define GPP_A8_IRQ 0x40 +#define GPP_A9_IRQ 0x41 +#define GPP_A10_IRQ 0x42 +#define GPP_A11_IRQ 0x43 +#define GPP_A12_IRQ 0x44 +#define GPP_A13_IRQ 0x45 +#define GPP_A14_IRQ 0x46 +#define GPP_A15_IRQ 0x47 +#define GPP_A16_IRQ 0x48 +#define GPP_A17_IRQ 0x49 +#define GPP_A18_IRQ 0x4a +#define GPP_A19_IRQ 0x4b + +/* Group S */ +#define GPP_S0_IRQ 0x5c +#define GPP_S1_IRQ 0x5d +#define GPP_S2_IRQ 0x5e +#define GPP_S3_IRQ 0x5f +#define GPP_S4_IRQ 0x60 +#define GPP_S5_IRQ 0x61 +#define GPP_S6_IRQ 0x62 +#define GPP_S7_IRQ 0x63 + +/* Group R */ +#define GPP_R0_IRQ 0x50 +#define GPP_R1_IRQ 0x51 +#define GPP_R2_IRQ 0x52 +#define GPP_R3_IRQ 0x53 +#define GPP_R4_IRQ 0x54 +#define GPP_R5_IRQ 0x55 +#define GPP_R6_IRQ 0x56 +#define GPP_R7_IRQ 0x57 + +/* Group H */ +#define GPP_H0_IRQ 0x70 +#define GPP_H1_IRQ 0x71 +#define GPP_H2_IRQ 0x72 +#define GPP_H3_IRQ 0x73 +#define GPP_H4_IRQ 0x74 +#define GPP_H5_IRQ 0x75 +#define GPP_H6_IRQ 0x76 +#define GPP_H7_IRQ 0x77 +#define GPP_H8_IRQ 0x18 +#define GPP_H9_IRQ 0x19 +#define GPP_H10_IRQ 0x1a +#define GPP_H11_IRQ 0x1b +#define GPP_H12_IRQ 0x1c +#define GPP_H13_IRQ 0x1d +#define GPP_H14_IRQ 0x1e +#define GPP_H15_IRQ 0x1f +#define GPP_H16_IRQ 0x20 +#define GPP_H17_IRQ 0x21 +#define GPP_H18_IRQ 0x22 +#define GPP_H19_IRQ 0x23 +#define GPP_H20_IRQ 0x24 +#define GPP_H21_IRQ 0x25 +#define GPP_H22_IRQ 0x26 +#define GPP_H23_IRQ 0x27 + +/* Group D */ +#define GPP_D0_IRQ 0x28 +#define GPP_D1_IRQ 0x29 +#define GPP_D2_IRQ 0x2a +#define GPP_D3_IRQ 0x2b +#define GPP_D4_IRQ 0x2c +#define GPP_D5_IRQ 0x2d +#define GPP_D6_IRQ 0x2e +#define GPP_D7_IRQ 0x2f +#define GPP_D8_IRQ 0x30 +#define GPP_D9_IRQ 0x31 +#define GPP_D10_IRQ 0x32 +#define GPP_D11_IRQ 0x33 +#define GPP_D12_IRQ 0x34 +#define GPP_D13_IRQ 0x35 +#define GPP_D14_IRQ 0x36 +#define GPP_D15_IRQ 0x37 +#define GPP_D16_IRQ 0x38 +#define GPP_D17_IRQ 0x39 +#define GPP_D18_IRQ 0x3a +#define GPP_D19_IRQ 0x3b +#define GPP_D20_IRQ 0x3c +#define GPP_D21_IRQ 0x3d +#define GPP_D22_IRQ 0x3e +#define GPP_D23_IRQ 0x3f + +#define GPP_VGPIO4_IRQ 0x58 +#define GPP_VGPIO39_IRQ 0x59 + +/* Group C */ +#define GPP_C0_IRQ 0x5a +#define GPP_C1_IRQ 0x5b +#define GPP_C2_IRQ 0x5c +#define GPP_C3_IRQ 0x5d +#define GPP_C4_IRQ 0x5e +#define GPP_C5_IRQ 0x5f +#define GPP_C6_IRQ 0x60 +#define GPP_C7_IRQ 0x61 +#define GPP_C8_IRQ 0x62 +#define GPP_C9_IRQ 0x63 +#define GPP_C10_IRQ 0x64 +#define GPP_C11_IRQ 0x65 +#define GPP_C12_IRQ 0x66 +#define GPP_C13_IRQ 0x67 +#define GPP_C14_IRQ 0x68 +#define GPP_C15_IRQ 0x69 +#define GPP_C16_IRQ 0x6a +#define GPP_C17_IRQ 0x6b +#define GPP_C18_IRQ 0x6c +#define GPP_C19_IRQ 0x6d +#define GPP_C20_IRQ 0x6e +#define GPP_C21_IRQ 0x6f +#define GPP_C22_IRQ 0x70 +#define GPP_C23_IRQ 0x71 + +/* Group D */ +#define GPD0_IRQ 0x64 +#define GPD1_IRQ 0x65 +#define GPD2_IRQ 0x66 +#define GPD3_IRQ 0x67 +#define GPD4_IRQ 0x68 +#define GPD5_IRQ 0x69 +#define GPD6_IRQ 0x6a +#define GPD7_IRQ 0x6b +#define GPD8_IRQ 0x6c +#define GPD9_IRQ 0x6d +#define GPD10_IRQ 0x6e + +/* Group E */ +#define GPP_E0_IRQ 0x72 +#define GPP_E1_IRQ 0x73 +#define GPP_E2_IRQ 0x74 +#define GPP_E3_IRQ 0x75 +#define GPP_E4_IRQ 0x76 +#define GPP_E5_IRQ 0x77 +#define GPP_E6_IRQ 0x18 +#define GPP_E7_IRQ 0x19 +#define GPP_E8_IRQ 0x1a +#define GPP_E9_IRQ 0x1b +#define GPP_E10_IRQ 0x1c +#define GPP_E11_IRQ 0x1d +#define GPP_E12_IRQ 0x1e +#define GPP_E13_IRQ 0x1f +#define GPP_E14_IRQ 0x20 +#define GPP_E15_IRQ 0x21 +#define GPP_E16_IRQ 0x22 +#define GPP_E17_IRQ 0x23 +#define GPP_E18_IRQ 0x24 +#define GPP_E19_IRQ 0x25 +#define GPP_E20_IRQ 0x26 +#define GPP_E21_IRQ 0x27 +#define GPP_E22_IRQ 0x28 +#define GPP_E23_IRQ 0x29 + +/* Group G */ +#define GPP_G0_IRQ 0x18 +#define GPP_G1_IRQ 0x19 +#define GPP_G2_IRQ 0x1a +#define GPP_G3_IRQ 0x1b +#define GPP_G4_IRQ 0x1c +#define GPP_G5_IRQ 0x1d +#define GPP_G6_IRQ 0x1e +#define GPP_G7_IRQ 0x1f + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xc0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1a0 +#define PAD_CFG_BASE 0x600 + +#define GPIORXSTATE_MASK 0x1 +#define GPIORXSTATE_SHIFT 1 +#define GPIOTXSTATE_MASK 0x1 +#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h new file mode 100644 index 0000000..187236e --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h @@ -0,0 +1,318 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ +#define _SOC_TIGERLAKE_GPIO_DEFS_TGL_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs.h> + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group B */ +#define GPP_B0_IRQ 0x18 +#define GPP_B1_IRQ 0x19 +#define GPP_B2_IRQ 0x1A +#define GPP_B3_IRQ 0x1B +#define GPP_B4_IRQ 0x1C +#define GPP_B5_IRQ 0x1D +#define GPP_B6_IRQ 0x1E +#define GPP_B7_IRQ 0x1F +#define GPP_B8_IRQ 0x20 +#define GPP_B9_IRQ 0x21 +#define GPP_B10_IRQ 0x22 +#define GPP_B11_IRQ 0x23 +#define GPP_B12_IRQ 0x24 +#define GPP_B13_IRQ 0x25 +#define GPP_B14_IRQ 0x26 +#define GPP_B15_IRQ 0x27 +#define GPP_B16_IRQ 0x28 +#define GPP_B17_IRQ 0x29 +#define GPP_B18_IRQ 0x2A +#define GPP_B19_IRQ 0x2B +#define GPP_B20_IRQ 0x2C +#define GPP_B21_IRQ 0x2D +#define GPP_B22_IRQ 0x2E +#define GPP_B23_IRQ 0x2F + +/* Group T */ +#define GPP_T0_IRQ 0x30 +#define GPP_T1_IRQ 0x31 +#define GPP_T2_IRQ 0x32 +#define GPP_T3_IRQ 0x33 +#define GPP_T4_IRQ 0x34 +#define GPP_T5_IRQ 0x35 +#define GPP_T6_IRQ 0x36 +#define GPP_T7_IRQ 0x37 +#define GPP_T8_IRQ 0x38 +#define GPP_T9_IRQ 0x39 +#define GPP_T10_IRQ 0x3A +#define GPP_T11IRQ 0x3B +#define GPP_T12_IRQ 0x3C +#define GPP_T13_IRQ 0x3D +#define GPP_T14_IRQ 0x3E +#define GPP_T15_IRQ 0x3F + +/* Group A */ +#define GPP_A0_IRQ 0x40 +#define GPP_A1_IRQ 0x41 +#define GPP_A2_IRQ 0x42 +#define GPP_A3_IRQ 0x43 +#define GPP_A4_IRQ 0x44 +#define GPP_A5_IRQ 0x45 +#define GPP_A6_IRQ 0x46 +#define GPP_A7_IRQ 0x47 +#define GPP_A8_IRQ 0x48 +#define GPP_A9_IRQ 0x49 +#define GPP_A10_IRQ 0x4A +#define GPP_A11_IRQ 0x4B +#define GPP_A12_IRQ 0x4C +#define GPP_A13_IRQ 0x4D +#define GPP_A14_IRQ 0x4E +#define GPP_A15_IRQ 0x4F +#define GPP_A16_IRQ 0x50 +#define GPP_A17_IRQ 0x51 +#define GPP_A18_IRQ 0x52 +#define GPP_A19_IRQ 0x53 +#define GPP_A20_IRQ 0x54 +#define GPP_A21_IRQ 0x55 +#define GPP_A22_IRQ 0x56 +#define GPP_A23_IRQ 0x57 + +/* Group R */ +#define GPP_R0_IRQ 0x58 +#define GPP_R1_IRQ 0x59 +#define GPP_R2_IRQ 0x5A +#define GPP_R3_IRQ 0x5B +#define GPP_R4_IRQ 0x5C +#define GPP_R5_IRQ 0x5D +#define GPP_R6_IRQ 0x5E +#define GPP_R7_IRQ 0x5F + + +/* Group D */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B + +/* Group S */ +#define GPP_S0_IRQ 0x6C +#define GPP_S1_IRQ 0x6D +#define GPP_S2_IRQ 0x6E +#define GPP_S3_IRQ 0x6F +#define GPP_S4_IRQ 0x70 +#define GPP_S5_IRQ 0x71 +#define GPP_S6_IRQ 0x72 +#define GPP_S7_IRQ 0x73 + +/* Group H */ +#define GPP_H0_IRQ 0x74 +#define GPP_H1_IRQ 0x75 +#define GPP_H2_IRQ 0x76 +#define GPP_H3_IRQ 0x77 +#define GPP_H4_IRQ 0x18 +#define GPP_H5_IRQ 0x19 +#define GPP_H6_IRQ 0x1A +#define GPP_H7_IRQ 0x1B +#define GPP_H8_IRQ 0x1C +#define GPP_H9_IRQ 0x1D +#define GPP_H10_IRQ 0x1E +#define GPP_H11_IRQ 0x1F +#define GPP_H12_IRQ 0x20 +#define GPP_H13_IRQ 0x21 +#define GPP_H14_IRQ 0x22 +#define GPP_H15_IRQ 0x23 +#define GPP_H16_IRQ 0x24 +#define GPP_H17_IRQ 0x25 +#define GPP_H18_IRQ 0x26 +#define GPP_H19_IRQ 0x27 +#define GPP_H20_IRQ 0x28 +#define GPP_H21_IRQ 0x29 +#define GPP_H22_IRQ 0x2A +#define GPP_H23_IRQ 0x2B + +/* Group D */ +#define GPP_D0_IRQ 0x2C +#define GPP_D1_IRQ 0x2D +#define GPP_D2_IRQ 0x2E +#define GPP_D3_IRQ 0x2F +#define GPP_D4_IRQ 0x30 +#define GPP_D5_IRQ 0x31 +#define GPP_D6_IRQ 0x32 +#define GPP_D7_IRQ 0x33 +#define GPP_D8_IRQ 0x34 +#define GPP_D9_IRQ 0x35 +#define GPP_D10_IRQ 0x36 +#define GPP_D11_IRQ 0x37 +#define GPP_D12_IRQ 0x38 +#define GPP_D13_IRQ 0x39 +#define GPP_D14_IRQ 0x3A +#define GPP_D15_IRQ 0x3B +#define GPP_D16_IRQ 0x3C +#define GPP_D17_IRQ 0x3D +#define GPP_D18_IRQ 0x3E +#define GPP_D19_IRQ 0x3F + + +/* Group U */ +#define GPP_U0_IRQ 0x40 +#define GPP_U1IRQ 0x41 +#define GPP_U2_IRQ 0x42 +#define GPP_U3_IRQ 0x43 +#define GPP_U4_IRQ 0x44 +#define GPP_U5_IRQ 0x45 +#define GPP_U6_IRQ 0x46 +#define GPP_U7_IRQ 0x47 +#define GPP_U8_IRQ 0x48 +#define GPP_U9_IRQ 0x49 +#define GPP_U10_IRQ 0x4A +#define GPP_U11_IRQ 0x4B +#define GPP_U12_IRQ 0x4C +#define GPP_U13_IRQ 0x4D +#define GPP_U14_IRQ 0x4E +#define GPP_U15_IRQ 0x4F +#define GPP_U16_IRQ 0x50 +#define GPP_U17_IRQ 0x51 +#define GPP_U18_IRQ 0x52 +#define GPP_U19_IRQ 0x53 + + +#define GPP_VGPIO4_IRQ 0x54 + +/* Group F */ +#define GPP_F0_IRQ 0x56 +#define GPP_F1_IRQ 0x57 +#define GPP_F2_IRQ 0x58 +#define GPP_F3_IRQ 0x59 +#define GPP_F4_IRQ 0x5A +#define GPP_F5_IRQ 0x5B +#define GPP_F6_IRQ 0x5C +#define GPP_F7_IRQ 0x5D +#define GPP_F8_IRQ 0x5E +#define GPP_F9_IRQ 0x5F +#define GPP_F10_IRQ 0x60 +#define GPP_F11_IRQ 0x61 +#define GPP_F12_IRQ 0x62 +#define GPP_F13_IRQ 0x63 +#define GPP_F14_IRQ 0x64 +#define GPP_F15_IRQ 0x65 +#define GPP_F16_IRQ 0x66 +#define GPP_F17_IRQ 0x67 +#define GPP_F18_IRQ 0x68 +#define GPP_F19_IRQ 0x69 +#define GPP_F20_IRQ 0x6A +#define GPP_F21_IRQ 0x6B +#define GPP_F22_IRQ 0x6C +#define GPP_F23_IRQ 0x6D + +/* Group C */ +#define GPP_C0_iIRQ 0x6E +#define GPP_C1_IRQ 0x6F +#define GPP_C2_IRQ 0x70 +#define GPP_C3_IRQ 0x71 +#define GPP_C4_IRQ 0x72 +#define GPP_C5_IRQ 0x73 +#define GPP_C6_IRQ 0x74 +#define GPP_C7_IRQ 0x75 +#define GPP_C8_IRQ 0x76 +#define GPP_C9_IRQ 0x77 +#define GPP_C10_IRQ 0x18 +#define GPP_C11_IRQ 0x19 +#define GPP_C12_IRQ 0x1A +#define GPP_C13_IRQ 0x1B +#define GPP_C14_IRQ 0x1C +#define GPP_C15_IRQ 0x1D +#define GPP_C16_IRQ 0x1E +#define GPP_C17_IRQ 0x1F +#define GPP_C18_IRQ 0x20 +#define GPP_C19_IRQ 0x21 +#define GPP_C20_IRQ 0x22 +#define GPP_C21_IRQ 0x23 +#define GPP_C22_IRQ 0x24 +#define GPP_C23_IRQ 0x25 + + + +/* Group E */ +#define GPP_E0_IRQ 0x26 +#define GPP_E1_IRQ 0x27 +#define GPP_E2_IRQ 0x28 +#define GPP_E3_IRQ 0x29 +#define GPP_E4_IRQ 0x30 +#define GPP_E5_IRQ 0x31 +#define GPP_E6_IRQ 0x32 +#define GPP_E7_IRQ 0x33 +#define GPP_E8_IRQ 0x34 +#define GPP_E9_IRQ 0x35 +#define GPP_E10_IRQ 0x36 +#define GPP_E11_IRQ 0x37 +#define GPP_E12_IRQ 0x38 +#define GPP_E13_IRQ 0x39 +#define GPP_E14_IRQ 0x3A +#define GPP_E15_IRQ 0x3B +#define GPP_E16_IRQ 0x3C +#define GPP_E17_IRQ 0x3D +#define GPP_E18_IRQ 0x3E +#define GPP_E19_IRQ 0x3F +#define GPP_E20_IRQ 0x40 +#define GPP_E21_IRQ 0x41 +#define GPP_E22_IRQ 0x42 +#define GPP_E23_IRQ 0x43 + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x180 +#define GPI_SMI_EN_0 0x1A0 +#define PAD_CFG_BASE 0x700 + +#define GPIORXSTATE_MASK 0x1 +#define GPIORXSTATE_SHIFT 1 +#define GPIOTXSTATE_MASK 0x1 +#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h index 62de63f..6b22223 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h @@ -14,372 +14,11 @@ */ #ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ #define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_ -/* - * Most of the fixed numbers and macros are based on the GPP groups. - * The GPIO groups are accessed through register blocks called - * communities. - */ -#define GPP_B 0x0 -#define GPP_T 0x1 -#define GPP_A 0x2 -#define GPP_R 0x3 -#define GPD 0x4 -#define GPP_S 0x5 -#define GPP_H 0x6 -#define GPP_D 0x7 -#define GPP_U 0x8 -#define GPP_F 0xA -#define GPP_C 0xB -#define GPP_E 0xC
-#define GPIO_MAX_NUM_PER_GROUP 27 - -#define COMM_0 0 -#define COMM_1 1 -#define COMM_2 2 -/* GPIO community 3 is not exposed to be used and hence is skipped. */ -#define COMM_4 3 -#define COMM_5 4 -/* - * GPIOs are ordered monotonically increasing to match ACPI/OS driver. - */ -/* Group B */ -#define GPP_B0 0 -#define GPP_B1 1 -#define GPP_B2 2 -#define GPP_B3 3 -#define GPP_B4 4 -#define GPP_B5 5 -#define GPP_B6 6 -#define GPP_B7 7 -#define GPP_B8 8 -#define GPP_B9 9 -#define GPP_B10 10 -#define GPP_B11 11 -#define GPP_B12 12 -#define GPP_B13 13 -#define GPP_B14 14 -#define GPP_B15 15 -#define GPP_B16 16 -#define GPP_B17 17 -#define GPP_B18 18 -#define GPP_B19 19 -#define GPP_B20 20 -#define GPP_B21 21 -#define GPP_B22 22 -#define GPP_B23 23 -#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ -#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ - -/* Group T */ -#define GPP_T0 26 -#define GPP_T1 27 -#define GPP_T2 28 -#define GPP_T3 29 -#define GPP_T4 30 -#define GPP_T5 31 -#define GPP_T6 32 -#define GPP_T7 33 -#define GPP_T8 34 -#define GPP_T9 35 -#define GPP_T10 36 -#define GPP_T11 37 -#define GPP_T12 38 -#define GPP_T13 39 -#define GPP_T14 40 -#define GPP_T15 41 - -/* Group A */ -#define GPP_A0 42 -#define GPP_A1 43 -#define GPP_A2 44 -#define GPP_A3 45 -#define GPP_A4 46 -#define GPP_A5 47 -#define GPP_A6 48 -#define GPP_A7 49 -#define GPP_A8 50 -#define GPP_A9 51 -#define GPP_A10 52 -#define GPP_A11 53 -#define GPP_A12 54 -#define GPP_A13 55 -#define GPP_A14 56 -#define GPP_A15 57 -#define GPP_A16 58 -#define GPP_A17 59 -#define GPP_A18 60 -#define GPP_A19 61 -#define GPP_A20 62 -#define GPP_A21 63 -#define GPP_A22 64 -#define GPP_A23 65 -#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ - -#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) - -/* Group S */ -#define GPP_S0 67 -#define GPP_S1 68 -#define GPP_S2 69 -#define GPP_S3 70 -#define GPP_S4 71 -#define GPP_S5 72 -#define GPP_S6 73 -#define GPP_S7 74 - -/* Group H */ -#define GPP_H0 75 -#define GPP_H1 76 -#define GPP_H2 77 -#define GPP_H3 78 -#define GPP_H4 79 -#define GPP_H5 80 -#define GPP_H6 81 -#define GPP_H7 82 -#define GPP_H8 83 -#define GPP_H9 84 -#define GPP_H10 85 -#define GPP_H11 86 -#define GPP_H12 87 -#define GPP_H13 88 -#define GPP_H14 89 -#define GPP_H15 90 -#define GPP_H16 91 -#define GPP_H17 92 -#define GPP_H18 93 -#define GPP_H19 94 -#define GPP_H20 95 -#define GPP_H21 96 -#define GPP_H22 97 -#define GPP_H23 98 - -/* Group D */ -#define GPP_D0 99 -#define GPP_D1 100 -#define GPP_D2 101 -#define GPP_D3 102 -#define GPP_D4 103 -#define GPP_D5 104 -#define GPP_D6 105 -#define GPP_D7 106 -#define GPP_D8 107 -#define GPP_D9 108 -#define GPP_D10 109 -#define GPP_D11 110 -#define GPP_D12 111 -#define GPP_D13 112 -#define GPP_D14 113 -#define GPP_D15 114 -#define GPP_D16 115 -#define GPP_D17 116 -#define GPP_D18 117 -#define GPP_D19 118 -#define GPP_GSPI2_CLK_LOOPBK 119 - -/* Group U */ -#define GPP_U0 120 -#define GPP_U1 121 -#define GPP_U2 122 -#define GPP_U3 123 -#define GPP_U4 124 -#define GPP_U5 125 -#define GPP_U6 126 -#define GPP_U7 127 -#define GPP_U8 128 -#define GPP_U9 129 -#define GPP_U10 130 -#define GPP_U11 131 -#define GPP_U12 132 -#define GPP_U13 133 -#define GPP_U14 134 -#define GPP_U15 135 -#define GPP_U16 136 -#define GPP_U17 137 -#define GPP_U18 138 -#define GPP_U19 139 -#define GPP_GSPI3_CLK_LOOPBK 140 -#define GPP_GSPI4_CLK_LOOPBK 141 -#define GPP_GSPI5_CLK_LOOPBK 142 -#define GPP_GSPI6_CLK_LOOPBK 143 - -/* Group VGPIO */ -#define CNV_BTEN 144 -#define CNV_BT_HOST_WAKEB 145 -#define CNV_BT_IF_SELECT 146 -#define vCNV_BT_UART_TXD 147 -#define vCNV_BT_UART_RXD 148 -#define vCNV_BT_UART_CTS_B 149 -#define vCNV_BT_UART_RTS_B 150 -#define vCNV_MFUART1_TXD 151 -#define vCNV_MFUART1_RXD 152 -#define vCNV_MFUART1_CTS_B 153 -#define vCNV_MFUART1_RTS_B 154 -#define vUART0_TXD 155 -#define vUART0_RXD 156 -#define vUART0_CTS_B 157 -#define vUART0_RTS_B 158 -#define vISH_UART0_TXD 159 -#define vISH_UART0_RXD 160 -#define vISH_UART0_CTS_B 161 -#define vISH_UART0_RTS_B 162 -#define vCNV_BT_I2S_BCLK 163 -#define vCNV_BT_I2S_WS_SYNC 164 -#define vCNV_BT_I2S_SDO 165 -#define vCNV_BT_I2S_SDI 166 -#define vI2S2_SCLK 167 -#define vI2S2_SFRM 168 -#define vI2S2_TXD 169 -#define vI2S2_RXD 170 - -#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1) - -/* Group GPD */ -#define GPD0 171 -#define GPD1 172 -#define GPD2 173 -#define GPD3 174 -#define GPD4 175 -#define GPD5 176 -#define GPD6 177 -#define GPD7 178 -#define GPD8 179 -#define GPD9 180 -#define GPD10 181 -#define GPD11 182 -#define GPD_INPUT3VSEL 183 -#define GPD_SLP_LANB 184 -#define GPD__SLP_SUSB 185 -#define GPD_WAKEB 186 -#define GPD_DRAM_RESETB 187 - -#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) - -/* Group C */ -#define GPP_C0 188 -#define GPP_C1 189 -#define GPP_C2 190 -#define GPP_C3 191 -#define GPP_C4 192 -#define GPP_C5 193 -#define GPP_C6 194 -#define GPP_C7 195 -#define GPP_C8 196 -#define GPP_C9 197 -#define GPP_C10 198 -#define GPP_C11 199 -#define GPP_C12 200 -#define GPP_C13 201 -#define GPP_C14 202 -#define GPP_C15 203 -#define GPP_C16 204 -#define GPP_C17 205 -#define GPP_C18 206 -#define GPP_C19 207 -#define GPP_C20 208 -#define GPP_C21 209 -#define GPP_C22 210 -#define GPP_C23 211 - -/* Group F */ -#define GPP_F0 212 -#define GPP_F1 213 -#define GPP_F2 214 -#define GPP_F3 215 -#define GPP_F4 216 -#define GPP_F5 217 -#define GPP_F6 218 -#define GPP_F7 219 -#define GPP_F8 220 -#define GPP_F9 221 -#define GPP_F10 222 -#define GPP_F11 223 -#define GPP_F12 224 -#define GPP_F13 225 -#define GPP_F14 226 -#define GPP_F15 227 -#define GPP_F16 228 -#define GPP_F17 229 -#define GPP_F18 230 -#define GPP_F19 231 -#define GPP_F20 232 -#define GPP_F21 233 -#define GPP_F22 234 -#define GPP_F23 235 -#define GPP_F_CLK_LOOPBK 236 - -/* Group HVCMOS */ -#define GPP_L_BKLTEN 237 -#define GPP_L_BKLTCTL 238 -#define GPP_L_VDDEN 239 -#define GPP_SYS_PWROK 240 -#define GPP_SYS_RESETB 241 -#define GPP_MLK_RSTB 242 - -/* Group E */ -#define GPP_E0 243 -#define GPP_E1 244 -#define GPP_E2 245 -#define GPP_E3 246 -#define GPP_E4 247 -#define GPP_E5 248 -#define GPP_E6 249 -#define GPP_E7 250 -#define GPP_E8 251 -#define GPP_E9 252 -#define GPP_E10 253 -#define GPP_E11 254 -#define GPP_E12 255 -#define GPP_E13 256 -#define GPP_E14 257 -#define GPP_E15 258 -#define GPP_E16 259 -#define GPP_E17 260 -#define GPP_E18 261 -#define GPP_E19 262 -#define GPP_E20 263 -#define GPP_E21 264 -#define GPP_E22 265 -#define GPP_E23 266 -#define GPP_E_CLK_LOOPBK 267 - -/* Group JTAG */ -#define GPP_JTAG_TDO 268 -#define GPP_JTAG_X 269 -#define GPP_JTAG_PRDYB 270 -#define GPP_JTAG_PREQB 271 -#define GPP_CPU_TRSTB 272 -#define GPP_JTAG_TDI 273 -#define GPP_JTAG_TMS 274 -#define GPP_JTAG_TCK 275 -#define GPP_DBG_PMODE 276 - -#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) - -/* Group R */ -#define GPP_R0 277 -#define GPP_R1 278 -#define GPP_R2 279 -#define GPP_R3 280 -#define GPP_R4 281 -#define GPP_R5 282 -#define GPP_R6 283 -#define GPP_R7 284 - -/* Group SPI */ -#define GPP_SPI_IO_2 285 -#define GPP_SPI_IO_3 286 -#define GPP_SPI_MOSI_IO_0 287 -#define GPP_SPI_MOSI_IO_1 288 -#define GPP_SPI_TPM_CSB 289 -#define GPP_SPI_FLASH_0_CSB 290 -#define GPP_SPI_FLASH_1_CSB 291 -#define GPP_SPI_CLK 292 -#define GPP_CLK_LOOPBK 293 - -#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) - -#define TOTAL_GPIO_COMM (COMM_5 + 1) -#define TOTAL_PADS 294 +#if CONFIG(SOC_INTEL_TIGERLAKE) + #include "gpio_soc_defs_tgl.h" +#else + #include "gpio_soc_defs_jsl.h" +#endif /* CONFIG_SOC_INTEL_TIGERLAKE */
#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h new file mode 100644 index 0000000..2ebbb63 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h @@ -0,0 +1,348 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_JSL_H_ +#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_JSL_H_ +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +#define GPP_F 0x0 +#define GPP_B 0x1 +#define GPP_A 0x2 +#define GPP_S 0x3 +#define GPP_R 0x4 +#define GPP_H 0x5 +#define GPP_D 0x6 +#define GPP_VGPIO 0x7 +#define GPP_C 0x8 +#define GPP_GPD 0x9 +#define GPP_E 0xA +#define GPP_G 0xB + +#define GPIO_NUM_GROUPS 12 +#define GPIO_MAX_NUM_PER_GROUP 24 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group F */ +#define GPP_F0 0 +#define GPP_F1 1 +#define GPP_F2 2 +#define GPP_F3 3 +#define GPP_F4 4 +#define GPP_F5 5 +#define GPP_F6 6 +#define GPP_F7 7 +#define GPP_F8 8 +#define GPP_F9 9 +#define GPP_F10 10 +#define GPP_F11 11 +#define GPP_F12 12 +#define GPP_F13 13 +#define GPP_F14 14 +#define GPP_F15 15 +#define GPP_F16 16 +#define GPP_F17 17 +#define GPP_F18 18 +#define GPP_F19 19 + +/* Group SPI */ +#define GPP_SPI_IO_2 20 +#define GPP_SPI_IO_3 21 +#define GPP_SPI_MOSI_IO_0 22 +#define GPP_SPI_MOSI_IO_1 23 +#define GPP_SPI_TPM_CSB 24 +#define GPP_SPI_FLASH_0_CSB 25 +#define GPP_SPI_FLASH_1_CSB 26 +#define GPP_SPI_CLK 27 +#define GPP_CLK_LOOPBK 28 + +/* Group B */ +#define GPP_B0 29 +#define GPP_B1 30 +#define GPP_B2 31 +#define GPP_B3 32 +#define GPP_B4 33 +#define GPP_B5 34 +#define GPP_B6 35 +#define GPP_B7 36 +#define GPP_B8 37 +#define GPP_B9 38 +#define GPP_B10 39 +#define GPP_B11 40 +#define GPP_B12 41 +#define GPP_B13 42 +#define GPP_B14 43 +#define GPP_B15 44 +#define GPP_B16 45 +#define GPP_B17 46 +#define GPP_B18 47 +#define GPP_B19 48 +#define GPP_B20 49 +#define GPP_B21 50 +#define GPP_B22 51 +#define GPP_B23 52 +#define GSPI0_CLK_LOOPBK 53 +#define GSPI1_CLK_LOOPBK 54 + +/* Group A */ +#define GPP_A0 55 +#define GPP_A1 56 +#define GPP_A2 57 +#define GPP_A3 58 +#define GPP_A4 59 +#define GPP_A5 60 +#define GPP_A6 61 +#define GPP_A7 62 +#define GPP_A8 63 +#define GPP_A9 64 +#define GPP_A10 65 +#define GPP_A11 66 +#define GPP_A12 67 +#define GPP_A13 68 +#define GPP_A14 69 +#define GPP_A15 70 +#define GPP_A16 71 +#define GPP_A17 72 +#define GPP_A18 73 +#define GPP_A19 74 +#define ESPI_CLK_LOOPBK 75 + +/* Group S */ +#define GPP_S0 76 +#define GPP_S1 77 +#define GPP_S2 78 +#define GPP_S3 79 +#define GPP_S4 80 +#define GPP_S5 81 +#define GPP_S6 82 +#define GPP_S7 83 + +/* Group R */ +#define GPP_R0 84 +#define GPP_R1 85 +#define GPP_R2 86 +#define GPP_R3 87 +#define GPP_R4 88 +#define GPP_R5 89 +#define GPP_R6 90 +#define GPP_R7 91 + +#define NUM_GPIO_COM0_PADS (GPP_R7 - GPP_F0 + 1) + +/* Group H */ +#define GPP_H0 92 +#define GPP_H1 93 +#define GPP_H2 94 +#define GPP_H3 95 +#define GPP_H4 96 +#define GPP_H5 97 +#define GPP_H6 98 +#define GPP_H7 99 +#define GPP_H8 100 +#define GPP_H9 101 +#define GPP_H10 102 +#define GPP_H11 103 +#define GPP_H12 104 +#define GPP_H13 105 +#define GPP_H14 106 +#define GPP_H15 107 +#define GPP_H16 108 +#define GPP_H17 109 +#define GPP_H18 110 +#define GPP_H19 111 +#define GPP_H20 112 +#define GPP_H21 113 +#define GPP_H22 114 +#define GPP_H23 115 + +/* Group D */ +#define GPP_D0 116 +#define GPP_D1 117 +#define GPP_D2 118 +#define GPP_D3 119 +#define GPP_D4 120 +#define GPP_D5 121 +#define GPP_D6 122 +#define GPP_D7 123 +#define GPP_D8 124 +#define GPP_D9 125 +#define GPP_D10 126 +#define GPP_D11 127 +#define GPP_D12 128 +#define GPP_D13 129 +#define GPP_D14 130 +#define GPP_D15 131 +#define GPP_D16 132 +#define GPP_D17 133 +#define GPP_D18 134 +#define GPP_D19 135 +#define GPP_D20 136 +#define GPP_D21 137 +#define GPP_D22 138 +#define GPP_D23 139 +#define GSPI2_CLK_LOOPBK 140 +#define SPI1_CLK_LOOPBK 141 + +/* Group VGPIO */ +#define VGPIO_0 142 +#define VGPIO_3 143 +#define VGPIO_4 144 +#define VGPIO_5 145 +#define VGPIO_6 146 +#define VGPIO_7 147 +#define VGPIO_8 148 +#define VGPIO_9 149 +#define VGPIO_10 150 +#define VGPIO_11 151 +#define VGPIO_12 152 +#define VGPIO_13 153 +#define VGPIO_18 154 +#define VGPIO_19 155 +#define VGPIO_20 156 +#define VGPIO_21 157 +#define VGPIO_22 158 +#define VGPIO_23 159 +#define VGPIO_24 160 +#define VGPIO_25 161 +#define VGPIO_30 162 +#define VGPIO_31 163 +#define VGPIO_32 164 +#define VGPIO_33 165 +#define VGPIO_34 166 +#define VGPIO_35 167 +#define VGPIO_36 168 +#define VGPIO_37 169 +#define VGPIO_39 170 + +/* Group C */ +#define GPP_C0 171 +#define GPP_C1 172 +#define GPP_C2 173 +#define GPP_C3 174 +#define GPP_C4 175 +#define GPP_C5 176 +#define GPP_C6 177 +#define GPP_C7 178 +#define GPP_C8 179 +#define GPP_C9 180 +#define GPP_C10 181 +#define GPP_C11 182 +#define GPP_C12 183 +#define GPP_C13 184 +#define GPP_C14 185 +#define GPP_C15 186 +#define GPP_C16 187 +#define GPP_C17 188 +#define GPP_C18 189 +#define GPP_C19 190 +#define GPP_C20 191 +#define GPP_C21 192 +#define GPP_C22 193 +#define GPP_C23 194 + +#define NUM_GPIO_COM1_PADS (GPP_C23 - GPP_H0 + 1) + +/* Group GPD */ +#define GPD0 195 +#define GPD1 196 +#define GPD2 197 +#define GPD3 198 +#define GPD4 199 +#define GPD5 200 +#define GPD6 201 +#define GPD7 202 +#define GPD8 203 +#define GPD9 204 +#define GPD10 205 +#define GPIO_INPUT3VSEL 206 +#define GPIO_SLP_SUSB 207 +#define GPIO_WAKEB 208 +#define GPIO_DRAM_RESETB 209 + +#define NUM_GPIO_COM2_PADS (GPIO_DRAM_RESETB - GPD0 + 1) + +/* Group E */ +#define GPIO_L_BKLTEN 210 +#define GPIO_L_BKLTCTRL 211 +#define GPIO_L_VDDEN 212 +#define GPIO_SYS_PWROK 213 +#define GPIO_SYS_RESETB 214 +#define GPIO_MKL_RSTB 215 +#define GPP_E0 216 +#define GPP_E1 217 +#define GPP_E2 218 +#define GPP_E3 219 +#define GPP_E4 220 +#define GPP_E5 221 +#define GPP_E6 222 +#define GPP_E7 223 +#define GPP_E8 224 +#define GPP_E9 225 +#define GPP_E10 226 +#define GPP_E11 227 +#define GPP_E12 228 +#define GPP_E13 229 +#define GPP_E14 230 +#define GPP_E15 231 +#define GPP_E16 232 +#define GPP_E17 233 +#define GPP_E18 234 +#define GPP_E19 235 +#define GPP_E20 236 +#define GPP_E21 237 +#define GPP_E22 238 +#define GPP_E23 239 +#define GPIO_JTAG_TDO 240 +#define GPIO_JTAGX 241 +#define GPIO_PRDYB 242 +#define GPIO_PREQB 243 +#define GPIO_CPU_TRSTB 244 +#define GPIO_JTAG_TDI 245 +#define GPIO_JTAG_TMS 246 +#define GPIO_JTAG_TCK 247 +#define GPIO_PMODE 248 +#define GPIO_VGPIO_LNK_DN_0 249 +#define GPIO_VGPIO_LNK_DN_1 250 +#define GPIO_VGPIO_LNK_DN_2 251 +#define GPIO_VGPIO_LNK_DN_3 252 + +#define NUM_GPIO_COM4_PADS (GPIO_VGPIO_LNK_DN_3 - GPIO_L_BKLTEN + 1) + +/* Group G */ +#define GPP_G0 253 +#define GPP_G1 254 +#define GPP_G2 255 +#define GPP_G3 256 +#define GPP_G4 257 +#define GPP_G5 258 +#define GPP_G6 259 +#define GPP_G7 260 + +#define NUM_GPIO_COM5_PADS (GPP_G7 - GPP_G0 + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS 261 + +#endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h new file mode 100644 index 0000000..f0b2764 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h @@ -0,0 +1,385 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ +#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_TGL_H_ +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + */ +#define GPP_B 0x0 +#define GPP_T 0x1 +#define GPP_A 0x2 +#define GPP_R 0x3 +#define GPD 0x4 +#define GPP_S 0x5 +#define GPP_H 0x6 +#define GPP_D 0x7 +#define GPP_U 0x8 +#define GPP_F 0xA +#define GPP_C 0xB +#define GPP_E 0xC + +#define GPIO_MAX_NUM_PER_GROUP 27 + +#define COMM_0 0 +#define COMM_1 1 +#define COMM_2 2 +/* GPIO community 3 is not exposed to be used and hence is skipped. */ +#define COMM_4 3 +#define COMM_5 4 +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ +/* Group B */ +#define GPP_B0 0 +#define GPP_B1 1 +#define GPP_B2 2 +#define GPP_B3 3 +#define GPP_B4 4 +#define GPP_B5 5 +#define GPP_B6 6 +#define GPP_B7 7 +#define GPP_B8 8 +#define GPP_B9 9 +#define GPP_B10 10 +#define GPP_B11 11 +#define GPP_B12 12 +#define GPP_B13 13 +#define GPP_B14 14 +#define GPP_B15 15 +#define GPP_B16 16 +#define GPP_B17 17 +#define GPP_B18 18 +#define GPP_B19 19 +#define GPP_B20 20 +#define GPP_B21 21 +#define GPP_B22 22 +#define GPP_B23 23 +#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */ +#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */ + +/* Group T */ +#define GPP_T0 26 +#define GPP_T1 27 +#define GPP_T2 28 +#define GPP_T3 29 +#define GPP_T4 30 +#define GPP_T5 31 +#define GPP_T6 32 +#define GPP_T7 33 +#define GPP_T8 34 +#define GPP_T9 35 +#define GPP_T10 36 +#define GPP_T11 37 +#define GPP_T12 38 +#define GPP_T13 39 +#define GPP_T14 40 +#define GPP_T15 41 + +/* Group A */ +#define GPP_A0 42 +#define GPP_A1 43 +#define GPP_A2 44 +#define GPP_A3 45 +#define GPP_A4 46 +#define GPP_A5 47 +#define GPP_A6 48 +#define GPP_A7 49 +#define GPP_A8 50 +#define GPP_A9 51 +#define GPP_A10 52 +#define GPP_A11 53 +#define GPP_A12 54 +#define GPP_A13 55 +#define GPP_A14 56 +#define GPP_A15 57 +#define GPP_A16 58 +#define GPP_A17 59 +#define GPP_A18 60 +#define GPP_A19 61 +#define GPP_A20 62 +#define GPP_A21 63 +#define GPP_A22 64 +#define GPP_A23 65 +#define GPP_A24 66 /* ESPI_CLK_LOOPBK */ + +#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1) + +/* Group S */ +#define GPP_S0 67 +#define GPP_S1 68 +#define GPP_S2 69 +#define GPP_S3 70 +#define GPP_S4 71 +#define GPP_S5 72 +#define GPP_S6 73 +#define GPP_S7 74 + +/* Group H */ +#define GPP_H0 75 +#define GPP_H1 76 +#define GPP_H2 77 +#define GPP_H3 78 +#define GPP_H4 79 +#define GPP_H5 80 +#define GPP_H6 81 +#define GPP_H7 82 +#define GPP_H8 83 +#define GPP_H9 84 +#define GPP_H10 85 +#define GPP_H11 86 +#define GPP_H12 87 +#define GPP_H13 88 +#define GPP_H14 89 +#define GPP_H15 90 +#define GPP_H16 91 +#define GPP_H17 92 +#define GPP_H18 93 +#define GPP_H19 94 +#define GPP_H20 95 +#define GPP_H21 96 +#define GPP_H22 97 +#define GPP_H23 98 + +/* Group D */ +#define GPP_D0 99 +#define GPP_D1 100 +#define GPP_D2 101 +#define GPP_D3 102 +#define GPP_D4 103 +#define GPP_D5 104 +#define GPP_D6 105 +#define GPP_D7 106 +#define GPP_D8 107 +#define GPP_D9 108 +#define GPP_D10 109 +#define GPP_D11 110 +#define GPP_D12 111 +#define GPP_D13 112 +#define GPP_D14 113 +#define GPP_D15 114 +#define GPP_D16 115 +#define GPP_D17 116 +#define GPP_D18 117 +#define GPP_D19 118 +#define GPP_GSPI2_CLK_LOOPBK 119 + +/* Group U */ +#define GPP_U0 120 +#define GPP_U1 121 +#define GPP_U2 122 +#define GPP_U3 123 +#define GPP_U4 124 +#define GPP_U5 125 +#define GPP_U6 126 +#define GPP_U7 127 +#define GPP_U8 128 +#define GPP_U9 129 +#define GPP_U10 130 +#define GPP_U11 131 +#define GPP_U12 132 +#define GPP_U13 133 +#define GPP_U14 134 +#define GPP_U15 135 +#define GPP_U16 136 +#define GPP_U17 137 +#define GPP_U18 138 +#define GPP_U19 139 +#define GPP_GSPI3_CLK_LOOPBK 140 +#define GPP_GSPI4_CLK_LOOPBK 141 +#define GPP_GSPI5_CLK_LOOPBK 142 +#define GPP_GSPI6_CLK_LOOPBK 143 + +/* Group VGPIO */ +#define CNV_BTEN 144 +#define CNV_BT_HOST_WAKEB 145 +#define CNV_BT_IF_SELECT 146 +#define vCNV_BT_UART_TXD 147 +#define vCNV_BT_UART_RXD 148 +#define vCNV_BT_UART_CTS_B 149 +#define vCNV_BT_UART_RTS_B 150 +#define vCNV_MFUART1_TXD 151 +#define vCNV_MFUART1_RXD 152 +#define vCNV_MFUART1_CTS_B 153 +#define vCNV_MFUART1_RTS_B 154 +#define vUART0_TXD 155 +#define vUART0_RXD 156 +#define vUART0_CTS_B 157 +#define vUART0_RTS_B 158 +#define vISH_UART0_TXD 159 +#define vISH_UART0_RXD 160 +#define vISH_UART0_CTS_B 161 +#define vISH_UART0_RTS_B 162 +#define vCNV_BT_I2S_BCLK 163 +#define vCNV_BT_I2S_WS_SYNC 164 +#define vCNV_BT_I2S_SDO 165 +#define vCNV_BT_I2S_SDI 166 +#define vI2S2_SCLK 167 +#define vI2S2_SFRM 168 +#define vI2S2_TXD 169 +#define vI2S2_RXD 170 + +#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1) + +/* Group GPD */ +#define GPD0 171 +#define GPD1 172 +#define GPD2 173 +#define GPD3 174 +#define GPD4 175 +#define GPD5 176 +#define GPD6 177 +#define GPD7 178 +#define GPD8 179 +#define GPD9 180 +#define GPD10 181 +#define GPD11 182 +#define GPD_INPUT3VSEL 183 +#define GPD_SLP_LANB 184 +#define GPD__SLP_SUSB 185 +#define GPD_WAKEB 186 +#define GPD_DRAM_RESETB 187 + +#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1) + +/* Group C */ +#define GPP_C0 188 +#define GPP_C1 189 +#define GPP_C2 190 +#define GPP_C3 191 +#define GPP_C4 192 +#define GPP_C5 193 +#define GPP_C6 194 +#define GPP_C7 195 +#define GPP_C8 196 +#define GPP_C9 197 +#define GPP_C10 198 +#define GPP_C11 199 +#define GPP_C12 200 +#define GPP_C13 201 +#define GPP_C14 202 +#define GPP_C15 203 +#define GPP_C16 204 +#define GPP_C17 205 +#define GPP_C18 206 +#define GPP_C19 207 +#define GPP_C20 208 +#define GPP_C21 209 +#define GPP_C22 210 +#define GPP_C23 211 + +/* Group F */ +#define GPP_F0 212 +#define GPP_F1 213 +#define GPP_F2 214 +#define GPP_F3 215 +#define GPP_F4 216 +#define GPP_F5 217 +#define GPP_F6 218 +#define GPP_F7 219 +#define GPP_F8 220 +#define GPP_F9 221 +#define GPP_F10 222 +#define GPP_F11 223 +#define GPP_F12 224 +#define GPP_F13 225 +#define GPP_F14 226 +#define GPP_F15 227 +#define GPP_F16 228 +#define GPP_F17 229 +#define GPP_F18 230 +#define GPP_F19 231 +#define GPP_F20 232 +#define GPP_F21 233 +#define GPP_F22 234 +#define GPP_F23 235 +#define GPP_F_CLK_LOOPBK 236 + +/* Group HVCMOS */ +#define GPP_L_BKLTEN 237 +#define GPP_L_BKLTCTL 238 +#define GPP_L_VDDEN 239 +#define GPP_SYS_PWROK 240 +#define GPP_SYS_RESETB 241 +#define GPP_MLK_RSTB 242 + +/* Group E */ +#define GPP_E0 243 +#define GPP_E1 244 +#define GPP_E2 245 +#define GPP_E3 246 +#define GPP_E4 247 +#define GPP_E5 248 +#define GPP_E6 249 +#define GPP_E7 250 +#define GPP_E8 251 +#define GPP_E9 252 +#define GPP_E10 253 +#define GPP_E11 254 +#define GPP_E12 255 +#define GPP_E13 256 +#define GPP_E14 257 +#define GPP_E15 258 +#define GPP_E16 259 +#define GPP_E17 260 +#define GPP_E18 261 +#define GPP_E19 262 +#define GPP_E20 263 +#define GPP_E21 264 +#define GPP_E22 265 +#define GPP_E23 266 +#define GPP_E_CLK_LOOPBK 267 + +/* Group JTAG */ +#define GPP_JTAG_TDO 268 +#define GPP_JTAG_X 269 +#define GPP_JTAG_PRDYB 270 +#define GPP_JTAG_PREQB 271 +#define GPP_CPU_TRSTB 272 +#define GPP_JTAG_TDI 273 +#define GPP_JTAG_TMS 274 +#define GPP_JTAG_TCK 275 +#define GPP_DBG_PMODE 276 + +#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1) + +/* Group R */ +#define GPP_R0 277 +#define GPP_R1 278 +#define GPP_R2 279 +#define GPP_R3 280 +#define GPP_R4 281 +#define GPP_R5 282 +#define GPP_R6 283 +#define GPP_R7 284 + +/* Group SPI */ +#define GPP_SPI_IO_2 285 +#define GPP_SPI_IO_3 286 +#define GPP_SPI_MOSI_IO_0 287 +#define GPP_SPI_MOSI_IO_1 288 +#define GPP_SPI_TPM_CSB 289 +#define GPP_SPI_FLASH_0_CSB 290 +#define GPP_SPI_FLASH_1_CSB 291 +#define GPP_SPI_CLK 292 +#define GPP_CLK_LOOPBK 293 + +#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS 294 + +#endif
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39113 )
Change subject: soc/intel/tigerlake: Add Jasper Lake GPIO definitions ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39113/1/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h:
https://review.coreboot.org/c/coreboot/+/39113/1/src/soc/intel/tigerlake/inc... PS1, Line 25: #define GPP_A 0x2 please, no space before tabs
https://review.coreboot.org/c/coreboot/+/39113/1/src/soc/intel/tigerlake/inc... PS1, Line 34: #define GPP_G 0xB please, no space before tabs
Hello Patrick Rudolph, Nick Vaccaro, Tim Wawrzynczak, Aamir Bohra, Justin TerAvest, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39113
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Add Jasper Lake GPIO definitions ......................................................................
soc/intel/tigerlake: Add Jasper Lake GPIO definitions
Define GPIO communities and groups for Jasper Lake. Since there are some difference between Tiger Lake and Jasper Lake, rename the existing GPIO definitions as Tiger Lake specific.
BUG=None TEST=Build the volteer and dedede mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I2ee2601f5761354c3ae24d0fb13f902d0d49496f --- M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/acpi/gpio.asl A src/soc/intel/tigerlake/acpi/gpio_jsl.asl A src/soc/intel/tigerlake/acpi/gpio_tgl.asl A src/soc/intel/tigerlake/gpio_jsl.c R src/soc/intel/tigerlake/gpio_tgl.c M src/soc/intel/tigerlake/include/soc/gpio_defs.h A src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h A src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h 12 files changed, 1,969 insertions(+), 866 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39113/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39113 )
Change subject: soc/intel/tigerlake: Add Jasper Lake GPIO definitions ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/acp... PS2, Line 15: : #if CONFIG(SOC_INTEL_TIGERLAKE) : #include "gpio_tgl.asl" : #else : #include "gpio_jsl.asl" : #endif These two files are nearly identical. The only differences I see are:
1) the _HID for the GPIO controllers 2) The GADD Method.
Would it make sense to factor these out into very small macros, so that the rest of the ASL is the same?
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/gpi... File src/soc/intel/tigerlake/gpio_jsl.c:
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/gpi... PS2, Line 125: , Just to clarify, TGL does not have a COMM_3?
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/gpi... PS2, Line 183: GPP_GPD nit: align this with the others
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/gpi... PS2, Line 185: TODO file a bug?
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39113 )
Change subject: soc/intel/tigerlake: Add Jasper Lake GPIO definitions ......................................................................
Patch Set 2:
Hi Karthik , there is a similar patch posted here: https://review.coreboot.org/c/coreboot/+/39111, can we pick that instead?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39113 )
Change subject: soc/intel/tigerlake: Add Jasper Lake GPIO definitions ......................................................................
Patch Set 2:
(3 comments)
Patch Set 2:
Hi Karthik , there is a similar patch posted here: https://review.coreboot.org/c/coreboot/+/39111, can we pick that instead?
Of course we can pick that CL. I was looking for the CL to configure GPIOs. Since I did not find one, I started working on it. We can drop this one in favor of your CL.
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/acp... PS2, Line 15: : #if CONFIG(SOC_INTEL_TIGERLAKE) : #include "gpio_tgl.asl" : #else : #include "gpio_jsl.asl" : #endif
These two files are nearly identical. The only differences I see are: […]
Lets us move the review to the other CL: https://review.coreboot.org/c/coreboot/+/39111
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/gpi... File src/soc/intel/tigerlake/gpio_jsl.c:
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/gpi... PS2, Line 125: ,
Just to clarify, TGL does not have a COMM_3?
Both TGL and JSL have COMM_3, but they are not exposed to be used.
https://review.coreboot.org/c/coreboot/+/39113/2/src/soc/intel/tigerlake/gpi... PS2, Line 185: TODO
file a bug?
The other CL: https://review.coreboot.org/c/coreboot/+/39111 seems to be handling this. So let us move all our discussion there.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39113 )
Change subject: soc/intel/tigerlake: Add Jasper Lake GPIO definitions ......................................................................
Patch Set 2:
Patch Set 2:
(3 comments)
Patch Set 2:
Hi Karthik , there is a similar patch posted here: https://review.coreboot.org/c/coreboot/+/39111, can we pick that instead?
Of course we can pick that CL. I was looking for the CL to configure JSL GPIOs. Since I did not find one, I started working on it. We can drop this one in favor of the CL you pointed out.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39113 )
Change subject: soc/intel/tigerlake: Add Jasper Lake GPIO definitions ......................................................................
Patch Set 2: Code-Review-1
Karthik Ramasubramanian has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/39113 )
Change subject: soc/intel/tigerlake: Add Jasper Lake GPIO definitions ......................................................................
Abandoned
The concerned support is landed in another CL
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Aamir Bohra (Code Review) -
build bot (Jenkins) (Code Review)
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Karthik Ramasubramanian (Code Review)
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Tim Wawrzynczak (Code Review)