Change in coreboot[master]: soc/intel/skylake: Use intel/common/uart driver

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19003 )

Change subject: soc/intel/skylake: Use intel/common/uart driver
......................................................................

soc/intel/skylake: Use intel/common/uart driver

Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/bootblock/bootblock.c
M src/soc/intel/skylake/bootblock/uart.c
M src/soc/intel/skylake/include/soc/bootblock.h
4 files changed, 9 insertions(+), 35 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/19003/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index a56d044..d68736b 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -49,6 +49,7 @@
    select SOC_INTEL_COMMON
    select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
    select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_UART
    select SOC_INTEL_COMMON_BLOCK_XHCI
    select SOC_INTEL_COMMON_LPSS_I2C
    select SOC_INTEL_COMMON_NHLT
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index c11d3d2..eb1ff5c 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -30,7 +30,7 @@
    pch_early_iorange_init();

if (IS_ENABLED(CONFIG_UART_DEBUG))
-		pch_uart_init();
+		soc_console_uart_init();
 }

void bootblock_soc_init(void)
diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c
index 4889428..5fad038 100644
--- a/src/soc/intel/skylake/bootblock/uart.c
+++ b/src/soc/intel/skylake/bootblock/uart.c
@@ -15,15 +15,13 @@
  * GNU General Public License for more details.
  */

-#include <arch/io.h>
 #include <console/uart.h>
-#include <device/pci_def.h>
-#include <stdint.h>
+#include <gpio.h>
+#include <intelblocks/uart.h>
 #include <soc/bootblock.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr.h>
-#include <soc/uart.h>
-#include <gpio.h>
+

/* UART2 pad configuration. Support RXD and TXD for now. */
 static const struct pad_config uart2_pads[] = {
@@ -31,35 +29,10 @@
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 };

-void pch_uart_init(void)
+void soc_console_uart_init(void)
 {
-	device_t dev = PCH_DEV_UART2;
-	u32 tmp;
-	u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE);
-
-	/* Set configured UART2 base address */
-	pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
-
-	/* Enable memory access and bus master */
-	tmp = pci_read_config32(dev, PCI_COMMAND);
-	tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, tmp);
-
-	/* Take UART2 out of reset */
-	tmp = read32(base + UART_RESET);
-	tmp |= UART_RESET_EN | UART_RESET_DMA_EN;
-	write32(base + UART_RESET, tmp);
-
-	/*
-	 * Set M and N divisor inputs and enable clock.
-	 * Main reference frequency to UART is:
-	 * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
-	 */
-	tmp = read32(base + UART_CLK);
-	tmp |= UART_CLK_EN | UART_CLK_UPDATE |
-		UART_CLK_DIV_N(UART_CLK_N_VAL) |
-		UART_CLK_DIV_M(UART_CLK_M_VAL);
-	write32(base + UART_CLK, tmp);
+	soc_uart_init(PCH_DEV_UART2,
+			uart_platform_base(CONFIG_UART_FOR_CONSOLE));

/* Put UART2 in byte access mode for 16550 compatibility */
    if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
index df81d3f..0a4c4af 100644
--- a/src/soc/intel/skylake/include/soc/bootblock.h
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -26,7 +26,7 @@
 void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 void bootblock_systemagent_early_init(void);
-void pch_uart_init(void);
+void soc_console_uart_init(void);

/* Bootblock post console init programing */
 void enable_smbus(void);