Change in coreboot[master]: soc/intel/*: Update microcode as specified for MP-init

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Nico Huber, Patrick Rudolph, Subrata Banik, Andrey Petrov, Nathaniel L Desimone.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 )

Change subject: soc/intel/*: Update microcode as specified for MP-init
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Patch Set 13:

(1 comment)

File src/soc/intel/alderlake/cpu.c:

https://review.coreboot.org/c/coreboot/+/49899/comment/92f1cbfe_df62e658 
PS13, Line 70: PRMRR
> Subrata, Nate, where is the sequence documented for platforms without […]

For ADL, there is a new MCHECK flow in the FSP, which apparently requires a microcode load immediately preceding it, therefore we have to use the MicrodeRegionBase UPD for ADL to have the FSP load the ucode patch a 2nd time.

For TGL, here are the snippets I can find in the BIOS core-uncore specs:
```
3.3.2.2 Loading Microcode Update on Application Processors (AP)

1. Immediately after wake up at the first time, such as during early MP initialization,
load, if current revision is ‘0’.
2. Must reload after memory initialization and PRMRR are configured.

3.3.2.3 Loading Microcode Update During POST
After caching is enabled and MTRR/PRMRR are properly configured, the BIOS is
required to reload the microcode update on all threads in order to activate certain
features, such as SGX.

3.3.4 
BIOS based second patch load:
Post memory initialization, System BIOS loads the microcode patch a second time
on all threads. This step takes care of loading the uncore component of the patch.
At this point, MCHECK executes to verify different aspects in the configurations, so
far.
```

For CML, #550049 says the following:
```
There are four MP initialization phases executed by the BSP and all APs.
• In Phase 1 the BIOS disables caching.
• In Phase 2 the BIOS loads the microcode update on all threads.
• In Phase 3 the BIOS configures and enables caching on all cores. The MTRRs,
PRMRR and DCU prefetcher configuration is copied from the BSP configuration.
• In Phase 4 BIOS executes reload of microcode update on all threads and initialize
the machine-check banks.
```

I don't see anything in there w/r/t timing of 2nd load & SMM relocation.