[L] Change in coreboot[master]: mb/intel: add Archer City CRB support

[Johnny Lin (Code Review)]

Attention is currently required from: Simon Chou, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez, Shelly Chang.

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 )

Change subject: mb/intel: add Archer City CRB support
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Patch Set 29:

(1 comment)

File src/mainboard/intel/archercity_crb/romstage.c:

https://review.coreboot.org/c/coreboot/+/71968/comment/52341b7d_94915af6 
PS27, Line 124: 	mupd->FspmConfig.serialDebugMsgLvl = 0x1;
> Hi Johnny/ Shelly, […]

In our current design we use VPD to configure FSP log level as well under xeon_sp/spr:
https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src...
I think we can remove line 115 to 119 for FSP log level and let VPD to configure them. Another point is that the SPR FSP log level mapping may not be the same as Client FSP log level mappings.