Change in coreboot[master]: mb/google/slippy: Convert variants to use override devicetree
Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39919 )
Change subject: mb/google/slippy: Convert variants to use override devicetree ......................................................................
mb/google/slippy: Convert variants to use override devicetree
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity.
Test: build all slippy variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will)
Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/google/slippy/Kconfig R src/mainboard/google/slippy/devicetree.cb A src/mainboard/google/slippy/variants/falco/overridetree.cb D src/mainboard/google/slippy/variants/leon/devicetree.cb A src/mainboard/google/slippy/variants/leon/overridetree.cb D src/mainboard/google/slippy/variants/peppy/devicetree.cb A src/mainboard/google/slippy/variants/peppy/overridetree.cb D src/mainboard/google/slippy/variants/wolf/devicetree.cb A src/mainboard/google/slippy/variants/wolf/overridetree.cb 9 files changed, 127 insertions(+), 424 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/39919/1
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 94ade7a..21659ab 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -48,9 +48,9 @@ string default "Google_Slippy"
-config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAX_CPUS int diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb similarity index 97% rename from src/mainboard/google/slippy/variants/falco/devicetree.cb rename to src/mainboard/google/slippy/devicetree.cb index 887ec4a..2474600 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -79,9 +79,6 @@ # Route all USB ports to XHCI per default register "xhci_default" = "1"
- # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013e0000" - device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 on end # Serial I/O DMA diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb new file mode 100644 index 0000000..a1c6f19 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -0,0 +1,20 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) + register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) + register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) + + device domain 0 on + + chip southbridge/intel/lynxpoint + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013e0000" + + end + end +end diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb deleted file mode 100644 index 27ce945..0000000 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ /dev/null @@ -1,158 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on # SMBus - chip drivers/i2c/rtd2132 - # Panel Power Timings (1 ms units) - # Note: the panel Tx timings are very - # different from the LVDS bridge - # Tx timing settings. Below is a mapping - # for RTD2132 -> Panel timings. - # T1 = T2 - # T2 = T8 + T10 + T12 - # T3 = T14 - # T4 = T15 - # T5 = T9 + T11 + T13 - # T6 = T3 - # T7 = T4 - register "t1" = "0x14" - register "t2" = "0xdc" - register "t3" = "0x0e" - register "t4" = "0x02" - register "t5" = "0xdc" - register "t6" = "0x14" - register "t7" = "0x208" - # LVDS Swap settings are normal. - register "lvds_swap" = "0" - # Enable Spread Sprectrum at 0.5% - register "sscg_percent" = "0x05" - device i2c 35 on end # (8bit address: 0x6A) - end # rtd2132 - end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb new file mode 100644 index 0000000..75bf2c6 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -0,0 +1,55 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + device domain 0 on + + chip southbridge/intel/lynxpoint + + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 1f.3 on # SMBus + chip drivers/i2c/rtd2132 + # Panel Power Timings (1 ms units) + # Note: the panel Tx timings are very + # different from the LVDS bridge + # Tx timing settings. Below is a mapping + # for RTD2132 -> Panel timings. + # T1 = T2 + # T2 = T8 + T10 + T12 + # T3 = T14 + # T4 = T15 + # T5 = T9 + T11 + T13 + # T6 = T3 + # T7 = T4 + register "t1" = "0x14" + register "t2" = "0xdc" + register "t3" = "0x0e" + register "t4" = "0x02" + register "t5" = "0xdc" + register "t6" = "0x14" + register "t7" = "0x208" + # LVDS Swap settings are normal. + register "lvds_swap" = "0" + # Enable Spread Sprectrum at 0.5% + register "sscg_percent" = "0x05" + device i2c 35 on end # (8bit address: 0x6A) + end # rtd2132 + end # SMBus + + end + end +end diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb deleted file mode 100644 index d5e797e..0000000 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ /dev/null @@ -1,130 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb new file mode 100644 index 0000000..3d3af98 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -0,0 +1,24 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + device domain 0 on + + chip southbridge/intel/lynxpoint + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + end + end +end diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb deleted file mode 100644 index ee0acca..0000000 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ /dev/null @@ -1,131 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) - register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) - register "gpu_panel_power_down_delay" = "500" # 50ms (T10) - register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb new file mode 100644 index 0000000..d59f290 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -0,0 +1,26 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) + register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) + register "gpu_panel_power_down_delay" = "500" # 50ms (T10) + register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) + + device domain 0 on + + chip southbridge/intel/lynxpoint + + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + end + end +end
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39919 )
Change subject: mb/google/slippy: Convert variants to use override devicetree ......................................................................
Patch Set 1: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... File src/mainboard/google/slippy/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 17: # Enable Panel and configure power delays : register "gpu_panel_port_select" = "1" # eDP : register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) : register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) : register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) : register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) : register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) Drop this, and let each variant specify the values?
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... File src/mainboard/google/slippy/variants/falco/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 4: register "gpu_panel_port_select" = "1" # eDP This is common for all four boards
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 17: blank line
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... File src/mainboard/google/slippy/variants/leon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 52: Blank line
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... File src/mainboard/google/slippy/variants/peppy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 21: blank line
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39919
to look at the new patch set (#2).
Change subject: mb/google/slippy: Convert variants to use override devicetree ......................................................................
mb/google/slippy: Convert variants to use override devicetree
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity.
Test: build all slippy variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will)
Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/google/slippy/Kconfig R src/mainboard/google/slippy/devicetree.cb A src/mainboard/google/slippy/variants/falco/overridetree.cb D src/mainboard/google/slippy/variants/leon/devicetree.cb A src/mainboard/google/slippy/variants/leon/overridetree.cb D src/mainboard/google/slippy/variants/peppy/devicetree.cb A src/mainboard/google/slippy/variants/peppy/overridetree.cb D src/mainboard/google/slippy/variants/wolf/devicetree.cb A src/mainboard/google/slippy/variants/wolf/overridetree.cb 9 files changed, 123 insertions(+), 432 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/39919/2
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39919 )
Change subject: mb/google/slippy: Convert variants to use override devicetree ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... File src/mainboard/google/slippy/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 17: # Enable Panel and configure power delays : register "gpu_panel_port_select" = "1" # eDP : register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) : register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) : register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) : register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) : register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6)
Drop this, and let each variant specify the values?
done. swore I did, must have snuck back in
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... File src/mainboard/google/slippy/variants/falco/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 4: register "gpu_panel_port_select" = "1" # eDP
This is common for all four boards
cleaner just to keep the entire panel section together IMO
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 17:
blank line
Done
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... File src/mainboard/google/slippy/variants/leon/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 52:
Blank line
Done
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... File src/mainboard/google/slippy/variants/peppy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 21:
blank line
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39919 )
Change subject: mb/google/slippy: Convert variants to use override devicetree ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... File src/mainboard/google/slippy/variants/falco/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39919/1/src/mainboard/google/slippy... PS1, Line 4: register "gpu_panel_port_select" = "1" # eDP
cleaner just to keep the entire panel section together IMO
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39919 )
Change subject: mb/google/slippy: Convert variants to use override devicetree ......................................................................
mb/google/slippy: Convert variants to use override devicetree
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity.
Test: build all slippy variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will)
Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240 Signed-off-by: Matt DeVillier matt.devillier@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39919 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/slippy/Kconfig R src/mainboard/google/slippy/devicetree.cb A src/mainboard/google/slippy/variants/falco/overridetree.cb D src/mainboard/google/slippy/variants/leon/devicetree.cb A src/mainboard/google/slippy/variants/leon/overridetree.cb D src/mainboard/google/slippy/variants/peppy/devicetree.cb A src/mainboard/google/slippy/variants/peppy/overridetree.cb D src/mainboard/google/slippy/variants/wolf/devicetree.cb A src/mainboard/google/slippy/variants/wolf/overridetree.cb 9 files changed, 123 insertions(+), 432 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 94ade7a..21659ab 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -48,9 +48,9 @@ string default "Google_Slippy"
-config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAX_CPUS int diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb similarity index 87% rename from src/mainboard/google/slippy/variants/falco/devicetree.cb rename to src/mainboard/google/slippy/devicetree.cb index 887ec4a..3d98d74 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -14,14 +14,6 @@ # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200"
- # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) - register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) - register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) - device cpu_cluster 0 on chip cpu/intel/haswell device lapic 0 on end @@ -79,9 +71,6 @@ # Route all USB ports to XHCI per default register "xhci_default" = "1"
- # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013e0000" - device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 on end # Serial I/O DMA diff --git a/src/mainboard/google/slippy/variants/falco/overridetree.cb b/src/mainboard/google/slippy/variants/falco/overridetree.cb new file mode 100644 index 0000000..c163202 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/overridetree.cb @@ -0,0 +1,19 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) + register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) + register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms (T5) + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms (T6) + + device domain 0 on + + chip southbridge/intel/lynxpoint + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013e0000" + end + end +end diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb deleted file mode 100644 index 27ce945..0000000 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ /dev/null @@ -1,158 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on # SMBus - chip drivers/i2c/rtd2132 - # Panel Power Timings (1 ms units) - # Note: the panel Tx timings are very - # different from the LVDS bridge - # Tx timing settings. Below is a mapping - # for RTD2132 -> Panel timings. - # T1 = T2 - # T2 = T8 + T10 + T12 - # T3 = T14 - # T4 = T15 - # T5 = T9 + T11 + T13 - # T6 = T3 - # T7 = T4 - register "t1" = "0x14" - register "t2" = "0xdc" - register "t3" = "0x0e" - register "t4" = "0x02" - register "t5" = "0xdc" - register "t6" = "0x14" - register "t7" = "0x208" - # LVDS Swap settings are normal. - register "lvds_swap" = "0" - # Enable Spread Sprectrum at 0.5% - register "sscg_percent" = "0x05" - device i2c 35 on end # (8bit address: 0x6A) - end # rtd2132 - end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/slippy/variants/leon/overridetree.cb b/src/mainboard/google/slippy/variants/leon/overridetree.cb new file mode 100644 index 0000000..f3b5c4a --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/overridetree.cb @@ -0,0 +1,54 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + device domain 0 on + + chip southbridge/intel/lynxpoint + + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 1f.3 on # SMBus + chip drivers/i2c/rtd2132 + # Panel Power Timings (1 ms units) + # Note: the panel Tx timings are very + # different from the LVDS bridge + # Tx timing settings. Below is a mapping + # for RTD2132 -> Panel timings. + # T1 = T2 + # T2 = T8 + T10 + T12 + # T3 = T14 + # T4 = T15 + # T5 = T9 + T11 + T13 + # T6 = T3 + # T7 = T4 + register "t1" = "0x14" + register "t2" = "0xdc" + register "t3" = "0x0e" + register "t4" = "0x02" + register "t5" = "0xdc" + register "t6" = "0x14" + register "t7" = "0x208" + # LVDS Swap settings are normal. + register "lvds_swap" = "0" + # Enable Spread Sprectrum at 0.5% + register "sscg_percent" = "0x05" + device i2c 35 on end # (8bit address: 0x6A) + end # rtd2132 + end # SMBus + end + end +end diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb deleted file mode 100644 index d5e797e..0000000 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ /dev/null @@ -1,130 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "5" # 400ms - register "gpu_panel_power_up_delay" = "400" # 40ms - register "gpu_panel_power_down_delay" = "150" # 15ms - register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb new file mode 100644 index 0000000..cd6a0df --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -0,0 +1,23 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "5" # 400ms + register "gpu_panel_power_up_delay" = "400" # 40ms + register "gpu_panel_power_down_delay" = "150" # 15ms + register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms + + device domain 0 on + + chip southbridge/intel/lynxpoint + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + end + end +end diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb deleted file mode 100644 index ee0acca..0000000 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ /dev/null @@ -1,131 +0,0 @@ -chip northbridge/intel/haswell - # IGD Displays - register "gfx" = "GMA_STATIC_DISPLAYS(0)" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Disable DisplayPort C Hotplug - register "gpu_dp_c_hotplug" = "0x00" - - # Enable HDMI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Set backlight PWM value for eDP - register "gpu_pch_backlight_pwm_hz" = "200" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) - register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) - register "gpu_panel_power_down_delay" = "500" # 50ms (T10) - register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) - - device cpu_cluster 0 on - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) - - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) - end - end - - device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - - chip southbridge/intel/lynxpoint - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" - - # Route all USB ports to XHCI per default - register "xhci_default" = "1" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address - end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end - end -end diff --git a/src/mainboard/google/slippy/variants/wolf/overridetree.cb b/src/mainboard/google/slippy/variants/wolf/overridetree.cb new file mode 100644 index 0000000..5ccca1d --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/overridetree.cb @@ -0,0 +1,25 @@ +chip northbridge/intel/haswell + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) + register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) + register "gpu_panel_power_down_delay" = "500" # 50ms (T10) + register "gpu_panel_power_backlight_on_delay" = "10" # 1ms (T8) + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms (T9) + + device domain 0 on + + chip southbridge/intel/lynxpoint + + register "sata_devslp_disable" = "0x1" + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + end + end +end
-
Angel Pons (Code Review) -
Matt DeVillier (Code Review)
-
Patrick Georgi (Code Review)