Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel skylake-sp. This SOC belongs to Xeon Scalable Processor family.
The skylake-sp FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,799 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/1
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 1:
(179 comments)
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 182: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 192: socket, stack, ioapic_id, ri->IoApicBase + 0x1000, gsi_base); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 193: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 668: PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 685: current += acpi_create_dmar_ds_pci(current, bus, CBDMA_DEV_NUM, cbdma_func_id); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 695: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 696: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 712: current += acpi_create_dmar_ds_pci(current, bus, VMD_DEV_NUM, VMD_FUNC_NUM); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 723: (*((volatile u32 *)(u32)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { // BIT 15 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 751: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 754: u64 vtd_mmio_cap = *(volatile u64 *)(unsigned int) (vtd_base + VTD_EXT_CAP_LOW); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 756: __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 770: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 771: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 773: u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 838: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 993: acpigen_emit_byte(type_flags); // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1012: const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1014: snprintf(rtname, sizeof(rtname), "RT%02x", (socket*MAX_IIO_STACK)+stack); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1026: if (socket == 0 && stack == 0) { // additional io resources on socket 0 bus 0 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1031: acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1032: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1033: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1034: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1042: if (socket == 0 && stack == 0) { // additional mem32 resources on socket 0 bus 0 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1044: (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_BASE_SIZE); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1046: (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, SPI_BASE_SIZE); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable", line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable", line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 385: res->base, res->limit, (bridge ? resource_type(res) : "")); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */ Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 391: } else { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 392: /* update bridge range from child bridge range */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 393: if (res->base < bridge->base) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 395: if (res->limit > bridge->limit) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 398: bridge->size = (bridge->limit - bridge->base + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... PS1, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... PS1, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... PS1, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 55: UINT8 SocketFirstBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 56: UINT8 SocketLastBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 57: UINT8 segmentSocket; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 58: UINT8 PcieSegment; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 60: UINT8 stackPresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 61: UINT8 StackBus[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 62: UINT8 M2PciePresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 63: UINT8 TotM3Kti; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 84: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 85: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 88: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 89: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 90: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 91: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 100: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 101: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 104: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 105: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 106: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 107: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 108: STACK_RES StackRes[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8] line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 444: /* find bus, device, and function number for socket ID UBOX device */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 && line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 452: bus_no, device_no, function_no, vendor_id, device_id); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 468: * Every 3b of the Node ID mapping register maps to a specific node line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 469: * Read the Node ID Mapping Register and find the node that matches line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 470: * the gid read from the Node ID configuration register (above). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) please, no space before tabs
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 499: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 512: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 514: else Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 550: PCU_DEV, PCU_CR1_FUN), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 551: PCU_CR1_BIOS_RESET_CPL_REG); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 2:
(179 comments)
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 182: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 192: socket, stack, ioapic_id, ri->IoApicBase + 0x1000, gsi_base); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 193: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 668: PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 685: current += acpi_create_dmar_ds_pci(current, bus, CBDMA_DEV_NUM, cbdma_func_id); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 695: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 696: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 712: current += acpi_create_dmar_ds_pci(current, bus, VMD_DEV_NUM, VMD_FUNC_NUM); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 723: (*((volatile u32 *)(u32)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { // BIT 15 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 751: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 754: u64 vtd_mmio_cap = *(volatile u64 *)(unsigned int) (vtd_base + VTD_EXT_CAP_LOW); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 756: __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 770: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 771: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 773: u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 838: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 993: acpigen_emit_byte(type_flags); // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1012: const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1014: snprintf(rtname, sizeof(rtname), "RT%02x", (socket*MAX_IIO_STACK)+stack); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1026: if (socket == 0 && stack == 0) { // additional io resources on socket 0 bus 0 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1031: acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1032: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1033: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1034: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1042: if (socket == 0 && stack == 0) { // additional mem32 resources on socket 0 bus 0 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1044: (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_BASE_SIZE); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1046: (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, SPI_BASE_SIZE); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable", line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable", line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 385: res->base, res->limit, (bridge ? resource_type(res) : "")); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */ Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 391: } else { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 392: /* update bridge range from child bridge range */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 393: if (res->base < bridge->base) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 395: if (res->limit > bridge->limit) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 398: bridge->size = (bridge->limit - bridge->base + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... PS2, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... PS2, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... PS2, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 55: UINT8 SocketFirstBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 56: UINT8 SocketLastBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 57: UINT8 segmentSocket; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 58: UINT8 PcieSegment; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 60: UINT8 stackPresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 61: UINT8 StackBus[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 62: UINT8 M2PciePresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 63: UINT8 TotM3Kti; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 84: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 85: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 88: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 89: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 90: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 91: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 100: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 101: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 104: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 105: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 106: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 107: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 108: STACK_RES StackRes[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8] line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 444: /* find bus, device, and function number for socket ID UBOX device */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 && line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 452: bus_no, device_no, function_no, vendor_id, device_id); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 468: * Every 3b of the Node ID mapping register maps to a specific node line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 469: * Read the Node ID Mapping Register and find the node that matches line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 470: * the gid read from the Node ID configuration register (above). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) please, no space before tabs
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 499: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 512: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 514: else Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 550: PCU_DEV, PCU_CR1_FUN), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 551: PCU_CR1_BIOS_RESET_CPL_REG); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
Hello Patrick Rudolph, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#3).
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel skylake-sp. This SOC belongs to Xeon Scalable Processor family.
The skylake-sp FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,809 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 3:
(169 comments)
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 701: hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 703: hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 720: current += acpi_create_dmar_ds_pci(current, bus, VMD_DEV_NUM, VMD_FUNC_NUM); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 764: u64 vtd_mmio_cap = *(volatile u64 *)(unsigned int) (vtd_base + VTD_EXT_CAP_LOW); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 783: u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 848: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1003: acpigen_emit_byte(type_flags); // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1022: const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1024: snprintf(rtname, sizeof(rtname), "RT%02x", (socket*MAX_IIO_STACK)+stack); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1036: if (socket == 0 && stack == 0) { // additional io resources on socket 0 bus 0 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1041: acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1042: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1043: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1044: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1052: if (socket == 0 && stack == 0) { // additional mem32 resources on socket 0 bus 0 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1054: (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_BASE_SIZE); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1056: (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, SPI_BASE_SIZE); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable", line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable", line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 385: res->base, res->limit, (bridge ? resource_type(res) : "")); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */ Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 391: } else { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 392: /* update bridge range from child bridge range */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 393: if (res->base < bridge->base) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 395: if (res->limit > bridge->limit) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 398: bridge->size = (bridge->limit - bridge->base + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... PS3, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... PS3, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... PS3, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 55: UINT8 SocketFirstBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 56: UINT8 SocketLastBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 57: UINT8 segmentSocket; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 58: UINT8 PcieSegment; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 60: UINT8 stackPresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 61: UINT8 StackBus[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 62: UINT8 M2PciePresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 63: UINT8 TotM3Kti; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 84: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 85: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 88: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 89: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 90: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 91: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 100: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 101: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 104: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 105: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 106: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 107: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 108: STACK_RES StackRes[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8] line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 444: /* find bus, device, and function number for socket ID UBOX device */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 && line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 452: bus_no, device_no, function_no, vendor_id, device_id); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 468: * Every 3b of the Node ID mapping register maps to a specific node line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 469: * Read the Node ID Mapping Register and find the node that matches line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 470: * the gid read from the Node ID configuration register (above). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) please, no space before tabs
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 499: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 512: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 514: else Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 550: PCU_DEV, PCU_CR1_FUN), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 551: PCU_CR1_BIOS_RESET_CPL_REG); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 3:
(12 comments)
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 182: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 192: socket, stack, ioapic_id, ri->IoApicBase + 0x1000, gsi_base);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 193: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 668: PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 685: current += acpi_create_dmar_ds_pci(current, bus, CBDMA_DEV_NUM, cbdma_func_id);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 695: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device;
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 696: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function;
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 712: current += acpi_create_dmar_ds_pci(current, bus, VMD_DEV_NUM, VMD_FUNC_NUM);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 723: (*((volatile u32 *)(u32)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { // BIT 15
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 751: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress;
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 754: u64 vtd_mmio_cap = *(volatile u64 *)(unsigned int) (vtd_base + VTD_EXT_CAP_LOW);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 756: __func__, socket, stack, bus, vtd_base, vtd_mmio_cap);
line over 96 characters
Done
Hello Patrick Rudolph, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#4).
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel skylake-sp. This SOC belongs to Xeon Scalable Processor family.
The skylake-sp FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,825 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 4:
(152 comments)
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable", line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable", line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 385: res->base, res->limit, (bridge ? resource_type(res) : "")); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */ Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 391: } else { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 392: /* update bridge range from child bridge range */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 393: if (res->base < bridge->base) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 395: if (res->limit > bridge->limit) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 398: bridge->size = (bridge->limit - bridge->base + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64 line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... PS4, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... PS4, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... PS4, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 55: UINT8 SocketFirstBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 56: UINT8 SocketLastBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 57: UINT8 segmentSocket; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 58: UINT8 PcieSegment; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 60: UINT8 stackPresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 61: UINT8 StackBus[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 62: UINT8 M2PciePresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 63: UINT8 TotM3Kti; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 84: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 85: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 88: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 89: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 90: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 91: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 100: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 101: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 104: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 105: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 106: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 107: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 108: STACK_RES StackRes[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8] line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 444: /* find bus, device, and function number for socket ID UBOX device */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 && line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 452: bus_no, device_no, function_no, vendor_id, device_id); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 468: * Every 3b of the Node ID mapping register maps to a specific node line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 469: * Read the Node ID Mapping Register and find the node that matches line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 470: * the gid read from the Node ID configuration register (above). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) please, no space before tabs
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 499: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 512: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 514: else Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 550: PCU_DEV, PCU_CR1_FUN), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 551: PCU_CR1_BIOS_RESET_CPL_REG); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10)); line over 96 characters
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 4:
(15 comments)
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 701: hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device;
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 703: hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function;
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 720: current += acpi_create_dmar_ds_pci(current, bus, VMD_DEV_NUM, VMD_FUNC_NUM);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 764: u64 vtd_mmio_cap = *(volatile u64 *)(unsigned int) (vtd_base + VTD_EXT_CAP_LOW);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 783: u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 848: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress;
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1003: acpigen_emit_byte(type_flags); // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1022: const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack];
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1024: snprintf(rtname, sizeof(rtname), "RT%02x", (socket*MAX_IIO_STACK)+stack);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1036: if (socket == 0 && stack == 0) { // additional io resources on socket 0 bus 0
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1041: acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1042: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1043: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1044: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1052: if (socket == 0 && stack == 0) { // additional mem32 resources on socket 0 bus 0
line over 96 characters
Done
Hello Patrick Rudolph, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#5).
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel skylake-sp. This SOC belongs to Xeon Scalable Processor family.
The skylake-sp FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,861 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 5:
(120 comments)
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 152: (res->flags & IORESOURCE_PREFETCH) ? \ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 171: (res->flags & IORESOURCE_PREFETCH) ? \ Avoid unnecessary line continuations
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 381: ((bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 382: IORESOURCE_PREFETCH | IORESOURCE_PCI64)) == line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 384: IORESOURCE_PREFETCH | IORESOURCE_PCI64))))) { line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 391: /* for 1st time update, overlading IORESOURCE_ASSIGNED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 392: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 396: } else { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 397: /* update bridge range from child bridge range */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 398: if (res->base < bridge->base) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 400: if (res->limit > bridge->limit) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 403: bridge->size = (bridge->limit - bridge->base + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 405: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 549: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 55: UINT8 SocketFirstBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 56: UINT8 SocketLastBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 57: UINT8 segmentSocket; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 58: UINT8 PcieSegment; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 60: UINT8 stackPresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 61: UINT8 StackBus[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 62: UINT8 M2PciePresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 63: UINT8 TotM3Kti; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 84: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 85: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 88: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 89: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 90: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 91: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 100: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 101: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 104: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 105: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 106: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 107: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 108: STACK_RES StackRes[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8] line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 444: /* find bus, device, and function number for socket ID UBOX device */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 && line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 452: bus_no, device_no, function_no, vendor_id, device_id); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 468: * Every 3b of the Node ID mapping register maps to a specific node line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 469: * Read the Node ID Mapping Register and find the node that matches line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 470: * the gid read from the Node ID configuration register (above). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc) please, no space before tabs
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 499: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 512: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 514: else Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 550: PCU_DEV, PCU_CR1_FUN), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 551: PCU_CR1_BIOS_RESET_CPL_REG); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/so... PS5, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; line over 96 characters
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 5:
(33 comments)
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res),
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 385: res->base, res->limit, (bridge ? resource_type(res) : ""));
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH))
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy));
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... PS4, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device,
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000)
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(),
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10;
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1);
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/un... PS4, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@9 PS5, Line 9: SOC Really? Skylake-SP is a SoC?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 5:
(14 comments)
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@7 PS5, Line 7: SkyLake Skylake
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@7 PS5, Line 7: Add Intel SkyLake Scalable Processor support Please use a prefix:
soc/intel: Add Skylake Scalable Processor support
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@13 PS5, Line 13: Remove.
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@13 PS5, Line 13: that will not be shared in public, at least for the time being. Please announce that to the mailing list, and ask, if we want such a non-working support (for everybody) in the tree.
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@14 PS5, Line 14: Tested how?
Please elaborate, why a new directory is needed, and it cannot be supported by extending the existing Skylake code.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/Kconfig File src/soc/intel/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/Kconfig@12 PS5, Line 12: source "src/soc/intel/skylake_sp/Kconfig" Sort.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 4: . Remove.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 5: . Remove.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 23: /* Global ACPI memory region. This region is used for passing information Please use the allowed comment style.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/iiostack.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 17: #define MAKE_IIO_DEV(id,rt) \ Why add the blank lines?
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 6: . Remove.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 29: Refer to Intel® C620 Series Chipset Platform Controller Hub section 20.11 Asterisk in the front.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 70: #define MAKE_LINK_DEV(id,uid) \ Please align the last .
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/uncore.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 4: . Remove.
Hello Patrick Rudolph, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#6).
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel skylake-sp. This SOC belongs to Xeon Scalable Processor family.
The skylake-sp FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,891 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/6
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 5:
(6 comments)
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 171: (res->flags & IORESOURCE_PREFETCH) ? \
Avoid unnecessary line continuations
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 381: ((bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM |
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 382: IORESOURCE_PREFETCH | IORESOURCE_PCI64)) ==
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ch... PS5, Line 549: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only)
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/in... PS5, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
line over 96 characters
Done
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 6:
(88 comments)
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ch... PS6, Line 393: /* for 1st time update, overlading IORESOURCE_ASSIGNED */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ch... PS6, Line 394: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ch... PS6, Line 398: } else { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ch... PS6, Line 399: /* update bridge range from child bridge range */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ch... PS6, Line 400: if (res->base < bridge->base) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ch... PS6, Line 402: if (res->limit > bridge->limit) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ch... PS6, Line 405: bridge->size = (bridge->limit - bridge->base + 1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ch... PS6, Line 407: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 55: UINT8 SocketFirstBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 56: UINT8 SocketLastBus; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 57: UINT8 segmentSocket; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 58: UINT8 PcieSegment; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 60: UINT8 stackPresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 61: UINT8 StackBus[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 62: UINT8 M2PciePresentBitmap; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 63: UINT8 TotM3Kti; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 84: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 85: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 88: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 89: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 90: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 91: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 100: UINT16 PciResourceIoBase; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 101: UINT16 PciResourceIoLimit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 104: UINT32 PciResourceMem32Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 105: UINT32 PciResourceMem32Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 106: UINT64 PciResourceMem64Base; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 107: UINT64 PciResourceMem64Limit; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 108: STACK_RES StackRes[MAX_IIO_STACK]; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8] line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 244: UINT8 RasModesSupported; //RAS modes that are supported by current memory population. line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/in... PS6, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 455: bus_no, device_no, function_no, vendor_id, device_id); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 458: device_no, function_no), (0x10 + (b * 4))); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 479: device_no, function_no), UNC_SOCKETID_UBOX_GID_OFFSET); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 482: if (nodeid == ((mapping >> (3 * i)) & 0x7)) { Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 492: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0) line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 497: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 498: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 504: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 507: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 509: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 517: if (i == 0) Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 518: start_busno = ((b1 >> (stack_id * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 519: else Too many leading tabs - consider code refactoring
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 520: start_busno = ((b2 >> ((i-1) * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 522: stack_id, start_busno, (r >> (i * 8)) & 0xff); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 555: PCU_DEV, PCU_CR1_FUN), line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 556: PCU_CR1_BIOS_RESET_CPL_REG); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 560: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 562: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 628: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 650: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT; line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 697: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 712: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 714: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 869: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 916: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 932: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 1021: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1, line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 1022: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT)); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 1061: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 1214: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 1216: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS); line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/so... PS6, Line 1259: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; line over 96 characters
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 6:
(4 comments)
The alignments in the ASL files need to be fixed and be consistent (tabs for indentation?).
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 159: int gsi_bases[] = {0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60}; Space after {?
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 52: PM1I, 64, // 0x15 - PM1 wake status bit Align?
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 25: * https://bugs.acpica.org/show_bug.cgi?id=1201 From the report:
Fixed in ACPICA version 20151124
Please update and remove the comment.
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 83: IRQ (Level, ActiveLow, Shared) {} \ Align.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 6:
(9 comments)
Thanks for the review!!
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@7 PS5, Line 7: Add Intel SkyLake Scalable Processor support
Please use a prefix: […]
Done
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@7 PS5, Line 7: SkyLake
Skylake
Skylake has several SKUs. This commits enables Skylake-SP (SP is short for Scalable Processor) which is a server SKU.
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@9 PS5, Line 9: SOC
Really? Skylake-SP is a SoC?
Yes, it integrates north bridge, and has other uncores, albeit it does not integrate PCH.
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@13 PS5, Line 13: that will not be shared in public, at least for the time being.
Please announce that to the mailing list, and ask, if we want such a non-working support (for everyb […]
This is first time for coreboot to support Xeon-SP. So it helps to get this initial support in, and we will optimize overtime (such as adding support for other processors of Xeon-SP family).
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@14 PS5, Line 14:
Tested how? […]
This is a new SKU. The exsiting Skylake directory is really for Skylake D SKU.
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 159: int gsi_bases[] = {0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60};
Space after {?
Done
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 52: PM1I, 64, // 0x15 - PM1 wake status bit
Align?
Done
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 25: * https://bugs.acpica.org/show_bug.cgi?id=1201
From the report: […]
Done
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 83: IRQ (Level, ActiveLow, Shared) {} \
Align.
Done
Hello Patrick Rudolph, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#7).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,917 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38548/7/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/7/src/soc/intel/skylake_sp/in... PS7, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/7/src/soc/intel/skylake_sp/in... PS7, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ line over 96 characters
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 7:
Patch Set 7:
(2 comments)
Not sure how to deal with some complain. Could someone offer advices?
Hello Patrick Rudolph, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#8).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,921 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38548/8/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/8/src/soc/intel/skylake_sp/in... PS8, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ line over 96 characters
https://review.coreboot.org/c/coreboot/+/38548/8/src/soc/intel/skylake_sp/in... PS8, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ line over 96 characters
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@13 PS5, Line 13: that will not be shared in public, at least for the time being.
This is first time for coreboot to support Xeon-SP. […]
Getting support into upstream coreboot implies that the coreboot community will have to maintain it. The last time we had a serverish Intel platform upstream (Broadwell-DE) we ended up dropping the support because of its binary situation, even though people still use it. So please take this request to discuss it on the mailing list seriously. If this ends up similarly to BDW-DE, you'll have wasted your and our time.
Of course, you could avoid any trouble by getting the binary released. At best, with a plan how long it will be maintained and what SKUs it will support.
Hello Patrick Rudolph, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#9).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,919 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/9
Hello Patrick Rudolph, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#10).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,908 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/10
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 10:
(9 comments)
https://review.coreboot.org/c/coreboot/+/38548/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/10//COMMIT_MSG@13 PS10, Line 13: that will not be shared in public, at least for the time being. please mention that SMM isn't working right now
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 943: void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, please move to acpigen.c
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 988: void acpigen_emit_qword(u64 data) please move to acpigen.c
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 995: void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, please move to acpigen.c
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 88: static void skxsp_pci_dev_iterator(struct bus *bus, it looks like some of those functions are copied from device/pci_* . Can you update the shared codebase to work with multiple domains?
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 578: return ""; that's not correct
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 756: //fast_spi_init(); is this still needed?
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 225: * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This whats 2.?
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 234: /* FSP takes care of MTRR settings */ is this still true?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 10: Code-Review-1
(2 comments)
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 18: #include <assert.h> : #include <arch/acpi.h> : #include <arch/cpu.h> : #include <arch/acpigen.h> : #include <arch/ioapic.h> : #include <arch/smp/mpspec.h> : #include <bootstate.h> : #include <string.h> : #include <cf9_reset.h> : #include <cpu/intel/turbo.h> : #include <cpu/x86/msr.h> : #include <cpu/x86/smm.h> : #include <intelblocks/acpi.h> : #include <intelblocks/msr.h> : #include <intelblocks/pmclib.h> : #include <device/pci.h> : #include <cbmem.h> : #include <soc/acpi.h> : #include <soc/cpu.h> : #include <soc/soc_util.h> : #include <soc/pm.h> : #include <soc/pmc.h> : #include <soc/pci_devs.h> : #include <soc/soc_util.h> : #include <soc/hob_iiouds.h> : #include <soc/hob_memmap.h> : #include "chip.h" Are you really using all of those includes ? Please include what you use. (same for the other files)
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 240: Please use 'Device ()' instead of 'Processor ()' the use of 'Processor ()' is deprecated -> https://review.coreboot.org/c/coreboot/+/37876
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 10:
(10 comments)
Rebased to upstream tip: e4d6c033fe (origin/master, origin/HEAD) Doc/mb/lenovo: Shrink picture for x301
Tested on TiogaPass server without regression observed.
https://review.coreboot.org/c/coreboot/+/38548/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/10//COMMIT_MSG@13 PS10, Line 13: that will not be shared in public, at least for the time being.
please mention that SMM isn't working right now
Done
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 18: #include <assert.h> : #include <arch/acpi.h> : #include <arch/cpu.h> : #include <arch/acpigen.h> : #include <arch/ioapic.h> : #include <arch/smp/mpspec.h> : #include <bootstate.h> : #include <string.h> : #include <cf9_reset.h> : #include <cpu/intel/turbo.h> : #include <cpu/x86/msr.h> : #include <cpu/x86/smm.h> : #include <intelblocks/acpi.h> : #include <intelblocks/msr.h> : #include <intelblocks/pmclib.h> : #include <device/pci.h> : #include <cbmem.h> : #include <soc/acpi.h> : #include <soc/cpu.h> : #include <soc/soc_util.h> : #include <soc/pm.h> : #include <soc/pmc.h> : #include <soc/pci_devs.h> : #include <soc/soc_util.h> : #include <soc/hob_iiouds.h> : #include <soc/hob_memmap.h> : #include "chip.h"
Are you really using all of those includes ? […]
Done
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 240:
Please use 'Device ()' instead of 'Processor ()' […]
The code I added/updated does not use Processor, actually with this patchset, there is no processor/socket devices declared in ACPI. Such is a to-do item noted. Right now the general code src/cpu/intel/common/acpi/cpu.asl declares _PR, which should be changed. Your commit added a comment, a step forward would be to update the common code base to move away from Processor ().
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 943: void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran,
please move to acpigen. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 988: void acpigen_emit_qword(u64 data)
please move to acpigen. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 995: void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags,
please move to acpigen. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 88: static void skxsp_pci_dev_iterator(struct bus *bus,
it looks like some of those functions are copied from device/pci_* . […]
I hope not to make the scope of initial commit bigger. That being said, let's discuss the details. Do you have a proposal in mind?
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 756: //fast_spi_init();
is this still needed?
Ditto!
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 225: * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
whats 2. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 234: /* FSP takes care of MTRR settings */
is this still true?
Done
Hello Patrick Rudolph, HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#11).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,787 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/11
Hello Patrick Rudolph, HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#12).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,787 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/12
Hello Patrick Rudolph, HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#13).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,787 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/13
Hello Patrick Rudolph, HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#14).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,777 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/14
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 14:
(1 comment)
Please include only what you use.
https://review.coreboot.org/c/coreboot/+/38548/14/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/14/src/soc/intel/skylake_sp/a... PS14, Line 25: msr looks like you don't use MSR, string, .... please check again (same for the other files)
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 14:
(1 comment)
Patch Set 14:
(1 comment)
Please include only what you use.
https://review.coreboot.org/c/coreboot/+/38548/14/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/14/src/soc/intel/skylake_sp/a... PS14, Line 25: msr
looks like you don't use MSR, string, .... […]
Done
Hello Patrick Rudolph, HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#15).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,775 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/15
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 15:
(24 comments)
https://review.coreboot.org/c/coreboot/+/38548/15/src/drivers/intel/fsp2_0/K... File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/15/src/drivers/intel/fsp2_0/K... PS15, Line 59: SOC_INTEL_SKYLAKE_SP Not yet
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/K... File src/soc/intel/skylake_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/K... PS15, Line 154: Do not change this value This kind of message makes me very curious about things. Sooo, what happens if I change it? Will the server start sprouting daisies or something? :D
On a more serious note, I guess this is for Intel QuickAssist Technology stuff?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/M... File src/soc/intel/skylake_sp/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/M... PS15, Line 23: subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm I'd move this line at the end of the block, as it's the only one that is conditional
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/iiostack.asl:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... PS15, Line 17: #define MAKE_IIO_DEV(id,rt) \ wait... that's a macro? O_o
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
PS15: Indenting could use some more tabs
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... PS15, Line 19: Datasheet? EDS? BIOS spec? BWG?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/uncore_irq.asl:
PS15: Do these have some sort of pattern, or could be grouped in logical blocks somehow?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... PS15, Line 50: Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Looks odd, is this correct?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/c... PS15, Line 147: msr1 Is this intentional?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/c... PS15, Line 305: printk(BIOS_ERR, "MP initialization failure.\n"); Can we survive if MP init failed?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 24: CPUID_SKYLAKESP_A0_A1 nit: add an underscore `_` to split SKYLAKESP:
CPUID_SKYLAKE_SP_A0_A1
(Also applies to the other CPUIDs)
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/gpio_fsp.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 86: (0x1 | (0x1 << 3)), ///< Set pad for both output and input This looks a bit odd
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 24: H Hm?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 102: PciResourceIoLimit poor things, they are flying away
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 149: CSI Link CSI... Isn't that QPI or UPI nowadays?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 249: SV_HOOKS Is this used?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 23: #define RDMSR(id) \ This could very well be a function returning the read msr
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 27: 08x 08?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/ramstage.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 16: double blank line
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 30: int dimm, int index); should fit in 96 chars
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/soc_config.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 16: double blank line
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 37: double blank line
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/s... File src/soc/intel/skylake_sp/smihandler.c:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/s... PS15, Line 24: die("Not implemented"); Do we need to die here?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/u... File src/soc/intel/skylake_sp/upd_display.c:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/u... PS15, Line 24: old->field, new->field) fits in 96 chars
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 15:
(20 comments)
Thanks for the review. This is first batch of answers. A few of them to be answered.
https://review.coreboot.org/c/coreboot/+/38548/15/src/drivers/intel/fsp2_0/K... File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/15/src/drivers/intel/fsp2_0/K... PS15, Line 59: SOC_INTEL_SKYLAKE_SP
Not yet
I do have a FSP 2.0 based SKYLAKE-SP FSP. It is an engineering build, Intel has no plan to make it public at the moment. This change is needed for me to build soc/intel/skylake_sp code and make TiogaPass image.
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/M... File src/soc/intel/skylake_sp/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/M... PS15, Line 23: subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
I'd move this line at the end of the block, as it's the only one that is conditional
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/iiostack.asl:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... PS15, Line 17: #define MAKE_IIO_DEV(id,rt) \
wait... […]
What's the question/ask?
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
PS15:
Indenting could use some more tabs
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... PS15, Line 19:
Datasheet? EDS? BIOS spec? BWG?
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/c... PS15, Line 147: msr1
Is this intentional?
Not sure what the question is. please clarify.
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/c... PS15, Line 305: printk(BIOS_ERR, "MP initialization failure.\n");
Can we survive if MP init failed?
If you look at other soc code which call mp_init_with_smm(), they all have similar logic. If MP init failed, we should bail out. That may be left as a later exercise that updates all callers of mp_init_with_smm().
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 24: CPUID_SKYLAKESP_A0_A1
nit: add an underscore `_` to split SKYLAKESP: […]
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/gpio_fsp.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 86: (0x1 | (0x1 << 3)), ///< Set pad for both output and input
This looks a bit odd
Why is this odd? With GpioDirInOut, we set two bits, for both output and input.
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 24: H
Hm?
src/include/device/pci_ids.h defined PCI_DEVICE_ID_INTEL_SKL_H_AUDIO. SKL_H means Skylake CPU with PCH. Here using the same to keep consistency.
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 102: PciResourceIoLimit
poor things, they are flying away
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 149: CSI Link
CSI... […]
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 249: SV_HOOKS
Is this used?
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 23: #define RDMSR(id) \
This could very well be a function returning the read msr
We need to print out the marco name. A function will not be able to accomplish that.
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 27: 08x
08?
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/ramstage.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 30: int dimm, int index);
should fit in 96 chars
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/soc_config.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 16:
double blank line
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 37:
double blank line
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/s... File src/soc/intel/skylake_sp/smihandler.c:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/s... PS15, Line 24: die("Not implemented");
Do we need to die here?
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/u... File src/soc/intel/skylake_sp/upd_display.c:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/u... PS15, Line 24: old->field, new->field)
fits in 96 chars
Done
Hello Patrick Rudolph, HAOUAS Elyes, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#16).
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
soc/intel: Add Intel SkyLake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is a proof-of-concept build. The binary will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,770 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/16
Anjaneya "Reddy" Chagam has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 16:
(3 comments)
Thx for the review. Pl see my comments inline.
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/K... File src/soc/intel/skylake_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/K... PS15, Line 154: Do not change this value
This kind of message makes me very curious about things. […]
Good point. This and IQAT_ENABLE are not relevant for Xeon SP SOC - will push new file with cleaned up Kconfig.
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/uncore_irq.asl:
PS15:
Do these have some sort of pattern, or could be grouped in logical blocks somehow?
They point to devices on Xeon SP IIO Stacks - will add comments indicating the devices they refer to and push changes
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... PS15, Line 50: Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
Looks odd, is this correct?
This is correct. [DMI0]: Legacy PCI Express Port 0 on PC00. I will add comments indicating devices they point to and push change.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 16:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/K... File src/soc/intel/skylake_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/K... PS15, Line 154: Do not change this value
Good point. […]
Ack
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/uncore_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... PS15, Line 50: Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
This is correct. [DMI0]: Legacy PCI Express Port 0 on PC00. […]
Ack.
Since the rest of the entries are aligned, I would suggest adding four spaces after the comma to align this one as well.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 16:
(12 comments)
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@7 PS5, Line 7: SkyLake
Skylake has several SKUs. […]
See latest patchset
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@9 PS5, Line 9: SOC
Yes, it integrates north bridge, and has other uncores, albeit it does not integrate PCH.
Done
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@14 PS5, Line 14:
This is a new SKU. The exsiting Skylake directory is really for Skylake D SKU.
I think "Skylake" is the only thing soc/intel/skylake/ and soc/intel/skylake_sp/ have in common
https://review.coreboot.org/c/coreboot/+/38548/16//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/16//COMMIT_MSG@7 PS16, Line 7: SkyLake The `L` should not be uppercase: Skylake
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/Kconfig File src/soc/intel/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/Kconfig@12 PS5, Line 12: source "src/soc/intel/skylake_sp/Kconfig"
Sort.
The list isn't sorted, though.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 23: /* Global ACPI memory region. This region is used for passing information
Please use the allowed comment style.
That is:
/* * Global ACPI...
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... PS16, Line 53: GPEI, 64, // 0x1D - GPE wake status bit maybe give these a little push with a tab?
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 29: Refer to Intel® C620 Series Chipset Platform Controller Hub section 20.11
Asterisk in the front.
Done
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... PS16, Line 27: Add (PCR_ITSS_PIRQA_ROUT, Looks like indentation became spaces again?
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/uncore_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... PS16, Line 18: u nit: Uncore
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/c... PS16, Line 374: if (!(res->flags & IORESOURCE_BRIDGE) || Can this be moved out into a function? It would avoid so many tabs
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/i... PS16, Line 24: Skylake Lewisburg?
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... PS16, Line 17: #include <assert.h> : #include <arch/acpi.h> : #include <arch/cpu.h> : #include <arch/acpigen.h> : #include <arch/ioapic.h> : #include <arch/smp/mpspec.h> : #include <string.h> : #include <cpu/intel/turbo.h> : #include <cpu/x86/smm.h> : #include <intelblocks/acpi.h> : #include <intelblocks/msr.h> : #include <intelblocks/pmclib.h> : #include <device/pci.h> : #include <cbmem.h> : #include <soc/acpi.h> : #include <soc/cpu.h> : #include <soc/soc_util.h> : #include <soc/pm.h> : #include <soc/pmc.h> : #include <soc/pci_devs.h> : #include <soc/hob_iiouds.h> : #include <soc/hob_memmap.h> : #include "chip.h" are you sure that you use all of those includes?
please include only what you use
(please also check the other files)
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#17).
Change subject: soc/intel: Add Intel Skylake Scalable Processor support ......................................................................
soc/intel: Add Intel Skylake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is a proof-of-concept build. The binary will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,622 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/17
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Skylake Scalable Processor support ......................................................................
Patch Set 16:
(8 comments)
Thanks. Updated version of patch set pushed.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/Kconfig File src/soc/intel/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/Kconfig@12 PS5, Line 12: source "src/soc/intel/skylake_sp/Kconfig"
The list isn't sorted, though.
Done
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... PS16, Line 17: #include <assert.h> : #include <arch/acpi.h> : #include <arch/cpu.h> : #include <arch/acpigen.h> : #include <arch/ioapic.h> : #include <arch/smp/mpspec.h> : #include <string.h> : #include <cpu/intel/turbo.h> : #include <cpu/x86/smm.h> : #include <intelblocks/acpi.h> : #include <intelblocks/msr.h> : #include <intelblocks/pmclib.h> : #include <device/pci.h> : #include <cbmem.h> : #include <soc/acpi.h> : #include <soc/cpu.h> : #include <soc/soc_util.h> : #include <soc/pm.h> : #include <soc/pmc.h> : #include <soc/pci_devs.h> : #include <soc/hob_iiouds.h> : #include <soc/hob_memmap.h> : #include "chip.h"
are you sure that you use all of those includes? […]
"chip.h" is needed. I have checked other files.
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 5: .
Remove.
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 23: /* Global ACPI memory region. This region is used for passing information
That is: […]
Done
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... PS16, Line 53: GPEI, 64, // 0x1D - GPE wake status bit
maybe give these a little push with a tab?
Done
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... PS16, Line 27: Add (PCR_ITSS_PIRQA_ROUT,
Looks like indentation became spaces again?
Yes, I am using spaces in ASL files to be consistent.
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/uncore_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/a... PS16, Line 18: u
nit: Uncore
Done
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/i... PS16, Line 24: Skylake
Lewisburg?
This refers to chipset. Let me update the comment more clearly.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Skylake Scalable Processor support ......................................................................
Patch Set 17:
(13 comments)
thanx for the reviews.
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@13 PS5, Line 13:
Remove.
Done
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@13 PS5, Line 13: that will not be shared in public, at least for the time being.
Getting support into upstream coreboot implies that the coreboot […]
Marking as resolved, as this was discussed in mailing list.
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@14 PS5, Line 14:
I think "Skylake" is the only thing soc/intel/skylake/ and soc/intel/skylake_sp/ have in common
The uncore is vastly different, but cpu core may be same.
https://review.coreboot.org/c/coreboot/+/38548/16//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/16//COMMIT_MSG@7 PS16, Line 7: SkyLake
The `L` should not be uppercase: Skylake
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/K... File src/soc/intel/skylake_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/K... PS15, Line 154: Do not change this value
Ack
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 4: .
Remove.
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/iiostack.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 17: #define MAKE_IIO_DEV(id,rt) \
Why add the blank lines?
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 6: .
Remove.
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 70: #define MAKE_LINK_DEV(id,uid) \
Please align the last .
Done
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/uncore.asl:
https://review.coreboot.org/c/coreboot/+/38548/5/src/soc/intel/skylake_sp/ac... PS5, Line 4: .
Remove.
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi/uncore_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/a... PS15, Line 50: Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
Ack. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 578: return "";
that's not correct
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/ramstage.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 16:
double blank line
Done
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#18).
Change subject: soc/intel: Add Intel Skylake Scalable Processor support ......................................................................
soc/intel: Add Intel Skylake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is a proof-of-concept build. The binary will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,599 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/18
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Skylake Scalable Processor support ......................................................................
Patch Set 18:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/5//COMMIT_MSG@13 PS5, Line 13: that will not be shared in public, at least for the time being.
Marking as resolved, as this was discussed in mailing list.
Done
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/c... PS10, Line 88: static void skxsp_pci_dev_iterator(struct bus *bus,
I hope not to make the scope of initial commit bigger. That being said, let's discuss the details. […]
We plan to improve the code in 3 phases: a. Get initial code in good shape. Such initial shape supports a Xeon-SP processor (eg. SKX-SP), it is good enough to boot into target OS. b. Extract Xeon-SP processor common code out. With such common code, one additional Xeon-SP processor will be supported, in addition to SKX-SP. c. Update generic code (such as device/pci_*) to work with multiple domains.
The being said, I went through the code, and made some changes: a. Got rid of soc_set_subsystem(). The generic one implemented in device/pci_device.c works fine. b. Reuse round() as defined in device/device.c.
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/16/src/soc/intel/skylake_sp/c... PS16, Line 374: if (!(res->flags & IORESOURCE_BRIDGE) ||
Can this be moved out into a function? It would avoid so many tabs
Done
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#19).
Change subject: soc/intel: Add Intel Skylake Scalable Processor support ......................................................................
soc/intel: Add Intel Skylake Scalable Processor support
This patch set adds support for Intel Skylake-SP. This processor SKU belongs to Xeon Scalable Processor family.
The Skylake-SP FSP is based on FSP 2.0. It is a proof-of-concept build. The binary will not be shared in public, at least for the time being.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,611 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/19
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#20).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.c.bak A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 51 files changed, 10,158 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/20
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#21).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.c.bak A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 51 files changed, 10,158 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/21
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#22).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.c.bak A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 51 files changed, 10,158 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/22
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#23).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.c.bak A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 51 files changed, 10,158 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/23
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#24).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.c.bak A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 51 files changed, 10,161 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/24
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#25).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/bootblock.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 50 files changed, 9,451 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/25
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 25:
(3 comments)
Thanks for the review. All the comments so far are addressed.
We plan to work on this code base (support for Xeon-SP processors and their OCP platforms) in 3 phases: Phase 1: initial code base. It supports the previous generation of Xeon-SP processor (Skylake-SP), and one OCP platform (TiogaPass). This patch set is verified to boot to target OS on several TiogaPass servers with slightly different configurations (such as CPU core count, PCIe config, socket count, etc.). Pending item of this phase is to merge this patch set into coreboot upstream. Phase 2. Support for current Xeon-SP processors. We are working on bring-up of current generation of Xeon-SP processor (Note that SKX-SP was in Mass Production as of 2018). The code base will be refactored/improved, it will support both Xeon-SP processors and multiple OCP platform (Most of the OCP platform are yet to be announced). This is the multi-company teams' focus right now. Phase 3. Nicer integration with coreboot common code. Through lessons learned from Xeon-SP code base, we will see what we could do to improve coreboot common code, if any.
Let us know if you have any further comments, we will address them as soon as we can.
Best, Jonathan
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/c... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/c... PS15, Line 147: msr1
Not sure what the question is. please clarify.
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/gpio_fsp.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 86: (0x1 | (0x1 << 3)), ///< Set pad for both output and input
Why is this odd? With GpioDirInOut, we set two bits, for both output and input.
Done
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/15/src/soc/intel/skylake_sp/i... PS15, Line 23: #define RDMSR(id) \
We need to print out the marco name. A function will not be able to accomplish that.
Done
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 25:
(20 comments)
thanks Jonathan I think the patch has been greatly improved. However I feel we need to better understand the logic around iio/bus resource assignment. It would be great to have at least that bit as a separate patch so we can review and better understand it.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/Kcon... PS21, Line 148: config HSUART_DEV : hex : default 0x1a : : config ENABLE_HSUART : depends on NON_LEGACY_UART_MODE : bool "Enable High-speed UART debug port selected by UART_FOR_CONSOLE." : default n : select CONSOLE_SERIAL : select DRIVERS_UART : select DRIVERS_UART_8250MEM : : config CONSOLE_UART_BASE_ADDRESS : depends on ENABLE_HSUART : hex "MMIO base address for UART" : default 0xd4000000 does skylake-sp has HSUART? I belive HSUART is part of some intel true SoC.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/Kcon... PS21, Line 169: config SKYLAKE_SP_CAR_NEM_ENHANCED : bool "Enhanced Non-evict mode" : depends on !FSP_CAR : default y : select SOC_INTEL_COMMON_BLOCK_CAR : select INTEL_CAR_NEM_ENHANCED : help : A current limitation of NEM (Non-Evict mode) is that code and data sizes : are derived from the requirement to not write out any modified cache line. : With NEM, if there is no physical memory behind the cached area, : the modified data will be lost and NEM results will be inconsistent. : ENHANCED NEM guarantees that modified data is always : kept in cache while clean data is replaced. we are using FSP_CAR and FSP-T. Unless there is plan to re-implement FSP-T, this is technically dead code
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/chip... PS21, Line 526: //show_devs_tree(dev, BIOS_SPEW, 0); please remove commented out code
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c.bak:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/chip... PS21, Line 1: * please remove this .bak file, I assume it a unwanted hitchhiker
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/cpu.... File src/soc/intel/xeon_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/cpu.... PS21, Line 47: //static char processor_name[64]; ditto
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/cpu.... PS21, Line 267: //southcluster_smm_enable_smi(); ditto
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/bootblock.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 22: void early_uart_init(void); is this function and file used?
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 20: /// This header file should be used together with : /// PCH GPIO lib in C and ASL. All defines used : /// must match both ASL/C syntax what is PCH GPIO lib?
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 245: #ifdef PCH_SERVER_BIOS_FLAG this looks unused/unset
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 32: UINT64 lets just use c99 fixed-width integers. What is this file? if it coming from intel, shouldn't it go to vendorcode?
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 19: same for this file
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 22: define RDMSR(id) \ this looks like DUMPMSR rather than RDMSR. rename?
also, by invoking this preprocessor macro we generate extra duplicated code. Why not turn this into a function? we can still have string macro name, just as a parameter
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 37: #define PCH_PCR_ADDRESS(Pid, Offset) \ : (P2SB_BAR | ((uint8_t)(Pid) << 16) | (uint16_t)(Offset)) you don't need this
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 44: #define DEV_FUNC_ENTER(dev) \ : printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ : __FILE__, __func__, __LINE__, dev_path(dev)) : : #define DEV_FUNC_EXIT(dev) \ : printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ : __func__, __LINE__, dev_path(dev)) : : #define FUNC_ENTER() \ : printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) : : #define FUNC_EXIT() \ : printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) I think we should drop these, now that we are done with debugging
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/rese... File src/soc/intel/xeon_sp/reset.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/rese... PS21, Line 21: void chipset_handle_reset(uint32_t status) : { : switch (status) { : case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ : die("Global Reset not implemented!\n"); : break; : default: : printk(BIOS_ERR, "unhandled reset type %x\n", status); : die("unknown reset type"); : break; : } : } it sounds like we are not trying to take action and actually issue a reset. Why?
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/roms... File src/soc/intel/xeon_sp/romstage.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/roms... PS21, Line 93: __weak void mainboard_memory_init_params(FSPM_UPD *mupd) : { : /* Do nothing */ : } remove? there is no need to declare empty function and call it here. what gives?
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... PS21, Line 170: void scan_dump_pci_devs(void) so what are we trying to achieve here? scan through PCIEX space and sww what is responding? if that is the case please just use pci_mmio_read_configX() variants
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... PS21, Line 180: DEFAULT_PCIEXBAR why we need something other than CONFIG_MMCONF_BASE_ADDRESS?
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... PS21, Line 599: if (total_delay >= max_delay) please use stopwatch_ family of functions (timer.h)
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... PS21, Line 868: void *addr = (void *) PCH_PCR_ADDRESS(PID_ITSS, reg); : uint8_t val = read8(addr); just pcr_read8(PID_ITSS, reg);
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 25:
I started xeonsp support from scratch: https://review.coreboot.org/c/coreboot/+/38840/2 Would it be possible to split and rebase your patch on top of it?
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#26).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 49 files changed, 9,365 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/26
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 26:
(19 comments)
Thanks for the review, Andrey.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/Kcon... PS21, Line 148: config HSUART_DEV : hex : default 0x1a : : config ENABLE_HSUART : depends on NON_LEGACY_UART_MODE : bool "Enable High-speed UART debug port selected by UART_FOR_CONSOLE." : default n : select CONSOLE_SERIAL : select DRIVERS_UART : select DRIVERS_UART_8250MEM : : config CONSOLE_UART_BASE_ADDRESS : depends on ENABLE_HSUART : hex "MMIO base address for UART" : default 0xd4000000
does skylake-sp has HSUART? I belive HSUART is part of some intel true SoC.
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/Kcon... PS21, Line 169: config SKYLAKE_SP_CAR_NEM_ENHANCED : bool "Enhanced Non-evict mode" : depends on !FSP_CAR : default y : select SOC_INTEL_COMMON_BLOCK_CAR : select INTEL_CAR_NEM_ENHANCED : help : A current limitation of NEM (Non-Evict mode) is that code and data sizes : are derived from the requirement to not write out any modified cache line. : With NEM, if there is no physical memory behind the cached area, : the modified data will be lost and NEM results will be inconsistent. : ENHANCED NEM guarantees that modified data is always : kept in cache while clean data is replaced.
we are using FSP_CAR and FSP-T. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/chip... PS21, Line 526: //show_devs_tree(dev, BIOS_SPEW, 0);
please remove commented out code
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c.bak:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/chip... PS21, Line 1: *
please remove this . […]
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/cpu.... File src/soc/intel/xeon_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/cpu.... PS21, Line 47: //static char processor_name[64];
ditto
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/cpu.... PS21, Line 267: //southcluster_smm_enable_smi();
ditto
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/bootblock.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 22: void early_uart_init(void);
is this function and file used?
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 20: /// This header file should be used together with : /// PCH GPIO lib in C and ASL. All defines used : /// must match both ASL/C syntax
what is PCH GPIO lib?
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 245: #ifdef PCH_SERVER_BIOS_FLAG
this looks unused/unset
It is used. See src/mainboard/ocp/tiogapass/romstage.c.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 32: UINT64
lets just use c99 fixed-width integers. […]
This file defined one of the HOB interface. It is not clear if Intel will add such as part of FSP header files. So for now we need to add such.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 19:
same for this file
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 22: define RDMSR(id) \
this looks like DUMPMSR rather than RDMSR. rename? […]
Prefer not to put the register name twice.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 37: #define PCH_PCR_ADDRESS(Pid, Offset) \ : (P2SB_BAR | ((uint8_t)(Pid) << 16) | (uint16_t)(Offset))
you don't need this
See src/soc/intel/xeon_sp/soc_util.c
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 44: #define DEV_FUNC_ENTER(dev) \ : printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ : __FILE__, __func__, __LINE__, dev_path(dev)) : : #define DEV_FUNC_EXIT(dev) \ : printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ : __func__, __LINE__, dev_path(dev)) : : #define FUNC_ENTER() \ : printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) : : #define FUNC_EXIT() \ : printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__)
I think we should drop these, now that we are done with debugging
We are not done with debugging. We should drop such when we finish phase 2.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/rese... File src/soc/intel/xeon_sp/reset.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/rese... PS21, Line 21: void chipset_handle_reset(uint32_t status) : { : switch (status) { : case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ : die("Global Reset not implemented!\n"); : break; : default: : printk(BIOS_ERR, "unhandled reset type %x\n", status); : die("unknown reset type"); : break; : } : }
it sounds like we are not trying to take action and actually issue a reset. […]
This is a stub code. We are going to implement this in future.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/roms... File src/soc/intel/xeon_sp/romstage.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/roms... PS21, Line 93: __weak void mainboard_memory_init_params(FSPM_UPD *mupd) : { : /* Do nothing */ : }
remove? there is no need to declare empty function and call it here. […]
They are here, so that mainboard can do some differentiation as needed.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... PS21, Line 170: void scan_dump_pci_devs(void)
so what are we trying to achieve here? scan through PCIEX space and sww what is responding? […]
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... PS21, Line 180: DEFAULT_PCIEXBAR
why we need something other than CONFIG_MMCONF_BASE_ADDRESS?
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... PS21, Line 868: void *addr = (void *) PCH_PCR_ADDRESS(PID_ITSS, reg); : uint8_t val = read8(addr);
just pcr_read8(PID_ITSS, reg);
Done
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 26:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 22: define RDMSR(id) \
Prefer not to put the register name twice.
I am just saying your preprocessor macro generates more code than needed. you probably want to do something like this:
void my_printmsr(unsigned int id, const char *name) { // your function logic goes here }
#define DUMP_MSR(id) \ { \ my_printmsr(id, #id); \ }
DUMP_MSR(abc); DUMP_MSR(xyz);
this way you will have less generated code and less binary code footprint.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 24: msr the macro should not modify variables outside its scope also why do not we just print "%08x%08x", msr.hi, msr.lo unconditionally?
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 37: #define PCH_PCR_ADDRESS(Pid, Offset) \ : (P2SB_BAR | ((uint8_t)(Pid) << 16) | (uint16_t)(Offset))
See src/soc/intel/xeon_sp/soc_util. […]
yeah I commented on that file. We need to use pcr_write()/pcr_read()
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/rese... File src/soc/intel/xeon_sp/reset.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/rese... PS21, Line 21: void chipset_handle_reset(uint32_t status) : { : switch (status) { : case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ : die("Global Reset not implemented!\n"); : break; : default: : printk(BIOS_ERR, "unhandled reset type %x\n", status); : die("unknown reset type"); : break; : } : }
This is a stub code. We are going to implement this in future.
if it is unimplemented, it is fine. But then it probably should just die unconditionally saying its unimplemented. If this function needs to behave in this specific way (ignore some reset request types and halt on others), please document why this is done in way. Otherwise it looks like copypasta.
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 26:
(7 comments)
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 38: /* Latency times in units of 1024ns. */ : #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e : #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76 : #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x94 : #define C_STATE_LATENCY_CONTROL_3_LIMIT 0xfa : #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x14c : #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x3f2 : : /* Power in units of mW */ : #define C1_POWER 0x3e8 : #define C3_POWER 0x1f4 : #define C6_POWER 0x15e : #define C7_POWER 0xc8 : #define C8_POWER 0xc8 : #define C9_POWER 0xc8 : #define C10_POWER 0xc8 : : /* Common Timer Copy (CTC) frequency - 24MHz. */ : #define CTC_FREQ 24000000 : : /* CPU bus clock is fixed at 100MHz */ : #define CPU_BCLK 100 : : #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ : (((1 << ((base)*5)) * (limit)) / 1000) : #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ : C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ : (IRTL_1024_NS >> 10)) : : int get_cpu_count(void); : void xeon_sp_init_cpus(struct device *dev); : : #endif : are these used anywhere?
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_fsp.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 21: #define RShiftU64(Operand, Count) (Operand >> Count) : #define LShiftU64(Operand, Count) (Operand << Count) : this looks unused
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 28: #define NO_REGISTER_FOR_PROPERTY (~0u) same here
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/incl... PS26, Line 33: #ifdef PCH_SERVER_BIOS_FLAG why do we need this condition?
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 245: #ifdef PCH_SERVER_BIOS_FLAG
It is used. See src/mainboard/ocp/tiogapass/romstage.c.
I do not understand this condition still. Why do we need it? If it is always defined why you need the condition?
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/incl... PS26, Line 35: define FORM_PCI_ADDR(bus, dev, fun, off) (((PCI_ENABLE)) | \ : ((bus & 0xFF) << 16)| \ : ((dev & 0x1F) << 11)| \ : ((fun & 0x07) << 8) | \ : ((off & 0xFF) << 0)) this is not used, remove
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/upd_... File src/soc/intel/xeon_sp/upd_display.c:
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/upd_... PS26, Line 23: #define DUMP_UPD(field) \ again I think it is generally bad idea for macro to touch variables outside its scope. This one is less harmful because it has no side-effect, but I'd really prefer it to be: #define DUMP_UPD(old, new, field);
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#27).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 49 files changed, 9,331 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/27
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 30:
(10 comments)
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/acpi... PS29, Line 808: if (size % 0x1000) // 4k align : size = ((MEM_BLK_COUNT * sizeof(MEM_BLK)) & (~0xfff)) + 0x1000; : can we use ALIGN(), ALIGN_UP() macros here?
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/cpu.... File src/soc/intel/xeon_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/cpu.... PS29, Line 233: int fixed_msrs[] = {0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; : for (int i = 0; i < sizeof(fixed_msrs)/sizeof(int); ++i) { : msr_t msr; : msr.lo = 0x05050505; : msr.hi = 0x05050505; : wrmsr(fixed_msrs[i], msr); : } : : // Patch ME Segment uncachable region 7F00 0000 - 7FFF FFFF : msr_t msr; : msr.lo = 0x7f000000; : msr.hi = 0x0; : wrmsr(0x206, msr); : msr.lo = 0xff000800; : msr.hi = 0x3fff; : wrmsr(0x207, msr); this looks like a kludge. Why we are hijacking MTRR setup that is done by common code?
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 290: if (i == 0) : continue; if we skip i==0, why not start the loop from 1 instead?
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 558: while ((reg & ((u32)1 << (pcode_init_bit-1))) == 0) { I suggest we use stopwatch() here to abort just in case. Otherwise this is a potential hard-hang
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 579: total_delay += step_delay; : if (total_delay >= max_delay) : break; same here, but I think I already mentioned this piece
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 587: u32 lets stick to c99 fixed width integers
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 768: if ((leaf_b.ecx & 0xff00) == 0x0200) : break; I feel a bit concerned for this loop. Would it be possible this never evaluates to true?
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 891: //assert(hob != NULL && hob_size != 0 && hob_size == sizeof(IIO_UDS)); remove commented out code?
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 929: sizeof(ids)/sizeof(int); ARRAY_SIZE()
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 1046: izeof(regs)/sizeof(uint64_t) ditto
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 32:
(13 comments)
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/cpu.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 38: /* Latency times in units of 1024ns. */ : #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e : #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76 : #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x94 : #define C_STATE_LATENCY_CONTROL_3_LIMIT 0xfa : #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x14c : #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x3f2 : : /* Power in units of mW */ : #define C1_POWER 0x3e8 : #define C3_POWER 0x1f4 : #define C6_POWER 0x15e : #define C7_POWER 0xc8 : #define C8_POWER 0xc8 : #define C9_POWER 0xc8 : #define C10_POWER 0xc8 : : /* Common Timer Copy (CTC) frequency - 24MHz. */ : #define CTC_FREQ 24000000 : : /* CPU bus clock is fixed at 100MHz */ : #define CPU_BCLK 100 : : #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ : (((1 << ((base)*5)) * (limit)) / 1000) : #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ : C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ : (IRTL_1024_NS >> 10)) : : int get_cpu_count(void); : void xeon_sp_init_cpus(struct device *dev); : : #endif :
are these used anywhere?
Not right now, they are needed for cstate support. Let's leave them here as they are needed sooner of later.
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_fsp.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 21: #define RShiftU64(Operand, Count) (Operand >> Count) : #define LShiftU64(Operand, Count) (Operand << Count) :
this looks unused
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 28: #define NO_REGISTER_FOR_PROPERTY (~0u)
same here
Done
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/incl... PS26, Line 33: #ifdef PCH_SERVER_BIOS_FLAG
why do we need this condition?
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 245: #ifdef PCH_SERVER_BIOS_FLAG
I do not understand this condition still. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 22: define RDMSR(id) \
I am just saying your preprocessor macro generates more code than needed. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 24: msr
the macro should not modify variables outside its scope […]
Done
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/incl... PS26, Line 35: define FORM_PCI_ADDR(bus, dev, fun, off) (((PCI_ENABLE)) | \ : ((bus & 0xFF) << 16)| \ : ((dev & 0x1F) << 11)| \ : ((fun & 0x07) << 8) | \ : ((off & 0xFF) << 0))
this is not used, remove
Done
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 290: if (i == 0) : continue;
if we skip i==0, why not start the loop from 1 instead?
Done
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 587: u32
lets stick to c99 fixed width integers
Done
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 929: sizeof(ids)/sizeof(int);
ARRAY_SIZE()
Done
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 1046: izeof(regs)/sizeof(uint64_t)
ditto
Done
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/upd_... File src/soc/intel/xeon_sp/upd_display.c:
https://review.coreboot.org/c/coreboot/+/38548/26/src/soc/intel/xeon_sp/upd_... PS26, Line 23: #define DUMP_UPD(field) \
again I think it is generally bad idea for macro to touch variables outside its scope. […]
Done
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 32:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/32/src/soc/intel/xeon_sp/unco... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/32/src/soc/intel/xeon_sp/unco... PS32, Line 18: include <cbmem.h> : #include <console/console.h> : #include <arch/acpi.h> : #include <arch/io.h> : #include <stdint.h> : #include <delay.h> : #include <device/device.h> : #include <device/pci.h> : #include <device/pci_ids.h> : #include <stdlib.h> : #include <string.h> : #include <romstage_handoff.h> : #include <timer.h> : #include <cpu/x86/lapic.h> : : #include <fsp/util.h> : #include <fsp/memory_init.h> : : #include <soc/soc_util.h> : #include <soc/iomap.h> : #include <soc/pci_devs.h> : #include <soc/ramstage.h> : #include <soc/acpi.h> please include Only what you use.
(same for the other files)
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#33).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 49 files changed, 9,176 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/33
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 33:
(10 comments)
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/acpi... PS29, Line 808: if (size % 0x1000) // 4k align : size = ((MEM_BLK_COUNT * sizeof(MEM_BLK)) & (~0xfff)) + 0x1000; :
can we use ALIGN(), ALIGN_UP() macros here?
Done
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/cpu.... File src/soc/intel/xeon_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/cpu.... PS29, Line 233: int fixed_msrs[] = {0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; : for (int i = 0; i < sizeof(fixed_msrs)/sizeof(int); ++i) { : msr_t msr; : msr.lo = 0x05050505; : msr.hi = 0x05050505; : wrmsr(fixed_msrs[i], msr); : } : : // Patch ME Segment uncachable region 7F00 0000 - 7FFF FFFF : msr_t msr; : msr.lo = 0x7f000000; : msr.hi = 0x0; : wrmsr(0x206, msr); : msr.lo = 0xff000800; : msr.hi = 0x3fff; : wrmsr(0x207, msr);
this looks like a kludge. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/cpu.... PS29, Line 233: int fixed_msrs[] = {0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f}; : for (int i = 0; i < sizeof(fixed_msrs)/sizeof(int); ++i) { : msr_t msr; : msr.lo = 0x05050505; : msr.hi = 0x05050505; : wrmsr(fixed_msrs[i], msr); : } : : // Patch ME Segment uncachable region 7F00 0000 - 7FFF FFFF : msr_t msr; : msr.lo = 0x7f000000; : msr.hi = 0x0; : wrmsr(0x206, msr); : msr.lo = 0xff000800; : msr.hi = 0x3fff; : wrmsr(0x207, msr);
this looks like a kludge. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/incl... PS21, Line 37: #define PCH_PCR_ADDRESS(Pid, Offset) \ : (P2SB_BAR | ((uint8_t)(Pid) << 16) | (uint16_t)(Offset))
yeah I commented on that file. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 558: while ((reg & ((u32)1 << (pcode_init_bit-1))) == 0) {
I suggest we use stopwatch() here to abort just in case. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 579: total_delay += step_delay; : if (total_delay >= max_delay) : break;
same here, but I think I already mentioned this piece
Done
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 768: if ((leaf_b.ecx & 0xff00) == 0x0200) : break;
I feel a bit concerned for this loop. […]
infinite loop concern is not really valid but that function is not needed, so dropped.
https://review.coreboot.org/c/coreboot/+/38548/29/src/soc/intel/xeon_sp/soc_... PS29, Line 891: //assert(hob != NULL && hob_size != 0 && hob_size == sizeof(IIO_UDS));
remove commented out code?
Done
https://review.coreboot.org/c/coreboot/+/38548/32/src/soc/intel/xeon_sp/unco... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/32/src/soc/intel/xeon_sp/unco... PS32, Line 18: include <cbmem.h> : #include <console/console.h> : #include <arch/acpi.h> : #include <arch/io.h> : #include <stdint.h> : #include <delay.h> : #include <device/device.h> : #include <device/pci.h> : #include <device/pci_ids.h> : #include <stdlib.h> : #include <string.h> : #include <romstage_handoff.h> : #include <timer.h> : #include <cpu/x86/lapic.h> : : #include <fsp/util.h> : #include <fsp/memory_init.h> : : #include <soc/soc_util.h> : #include <soc/iomap.h> : #include <soc/pci_devs.h> : #include <soc/ramstage.h> : #include <soc/acpi.h>
please include Only what you use. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/32/src/soc/intel/xeon_sp/unco... PS32, Line 18: include <cbmem.h> : #include <console/console.h> : #include <arch/acpi.h> : #include <arch/io.h> : #include <stdint.h> : #include <delay.h> : #include <device/device.h> : #include <device/pci.h> : #include <device/pci_ids.h> : #include <stdlib.h> : #include <string.h> : #include <romstage_handoff.h> : #include <timer.h> : #include <cpu/x86/lapic.h> : : #include <fsp/util.h> : #include <fsp/memory_init.h> : : #include <soc/soc_util.h> : #include <soc/iomap.h> : #include <soc/pci_devs.h> : #include <soc/ramstage.h> : #include <soc/acpi.h>
please include Only what you use. […]
Done
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 33:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/rese... File src/soc/intel/xeon_sp/reset.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/rese... PS21, Line 21: void chipset_handle_reset(uint32_t status) : { : switch (status) { : case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ : die("Global Reset not implemented!\n"); : break; : default: : printk(BIOS_ERR, "unhandled reset type %x\n", status); : die("unknown reset type"); : break; : } : }
if it is unimplemented, it is fine. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/soc_... PS21, Line 599: if (total_delay >= max_delay)
please use stopwatch_ family of functions (timer. […]
Done
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 33:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/33/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/33/src/soc/intel/xeon_sp/acpi... PS33, Line 18: #include <assert.h> : #include <arch/acpi.h> : #include <arch/cpu.h> : #include <arch/acpigen.h> : #include <arch/ioapic.h> : #include <arch/smp/mpspec.h> : #include <string.h> : #include <cpu/intel/turbo.h> : #include <cpu/x86/smm.h> : #include <intelblocks/acpi.h> : #include <intelblocks/msr.h> : #include <intelblocks/pmclib.h> : #include <device/pci.h> : #include <cbmem.h> : #include <soc/acpi.h> : #include <soc/cpu.h> : #include <soc/soc_util.h> : #include <soc/pm.h> : #include <soc/pmc.h> : #include <soc/pci_devs.h> : #include <soc/hob_iiouds.h> : #include <soc/hob_memmap.h> : #include "chip.h" Are you using all of those includes ?
Please clean and include only what you use. (Please check the other files)
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 33: Code-Review-1
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#34).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated accordintly to add support for other Xeon-SP processors, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 49 files changed, 9,123 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/34
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/33/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/33/src/soc/intel/xeon_sp/acpi... PS33, Line 18: #include <assert.h> : #include <arch/acpi.h> : #include <arch/cpu.h> : #include <arch/acpigen.h> : #include <arch/ioapic.h> : #include <arch/smp/mpspec.h> : #include <string.h> : #include <cpu/intel/turbo.h> : #include <cpu/x86/smm.h> : #include <intelblocks/acpi.h> : #include <intelblocks/msr.h> : #include <intelblocks/pmclib.h> : #include <device/pci.h> : #include <cbmem.h> : #include <soc/acpi.h> : #include <soc/cpu.h> : #include <soc/soc_util.h> : #include <soc/pm.h> : #include <soc/pmc.h> : #include <soc/pci_devs.h> : #include <soc/hob_iiouds.h> : #include <soc/hob_memmap.h> : #include "chip.h"
Are you using all of those includes ? […]
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 37:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/37//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/37//COMMIT_MSG@14 PS37, Line 14: accordintly accordingly
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 37:
(1 comment)
Patch Set 37:
(1 comment)
Will wait for 24 hours to gather other comments before submitting this commit message change.
https://review.coreboot.org/c/coreboot/+/38548/37//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38548/37//COMMIT_MSG@14 PS37, Line 14: accordintly
accordingly
Done
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 37:
(6 comments)
thx
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/boot... PS37, Line 18: #include <cpu/x86/mtrr.h> seems to be not used
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/boot... PS37, Line 25: include <timestamp.h> not used ? please check the other includes
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.h:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/chip... PS37, Line 23: #include <commonlib/helpers.h> : #include <intelblocks/cfg.h> : #include <intelblocks/gspi.h> : #include <soc/gpe.h> : #include <soc/irq.h> : #include <soc/pci_devs.h> maybe some are not used
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... PS37, Line 24: uint16_t needs <stdint.h>
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... PS37, Line 21: #include <arch/acpi.h> : #include <device/mmio.h> : #include <soc/gpe.h> : #include <soc/iomap.h> : #include <soc/pmc.h> please check
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/smih... File src/soc/intel/xeon_sp/smihandler.c:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/smih... PS37, Line 18: #include <arch/hlt.h> not used ?
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#38).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 49 files changed, 9,115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/38
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 38: Code-Review+1
Thx
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 38:
(6 comments)
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/boot... PS37, Line 18: #include <cpu/x86/mtrr.h>
seems to be not used
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/boot... PS37, Line 25: include <timestamp.h>
not used ? […]
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.h:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/chip... PS37, Line 23: #include <commonlib/helpers.h> : #include <intelblocks/cfg.h> : #include <intelblocks/gspi.h> : #include <soc/gpe.h> : #include <soc/irq.h> : #include <soc/pci_devs.h>
maybe some are not used
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... PS37, Line 24: uint16_t
needs <stdint. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... PS37, Line 21: #include <arch/acpi.h> : #include <device/mmio.h> : #include <soc/gpe.h> : #include <soc/iomap.h> : #include <soc/pmc.h>
please check
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/smih... File src/soc/intel/xeon_sp/smihandler.c:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/smih... PS37, Line 18: #include <arch/hlt.h>
not used ?
Done
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 38:
(5 comments)
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/boot... PS37, Line 18: #include <cpu/x86/mtrr.h>
seems to be not used
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/boot... PS37, Line 25: include <timestamp.h>
not used ? […]
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.h:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/chip... PS37, Line 23: #include <commonlib/helpers.h> : #include <intelblocks/cfg.h> : #include <intelblocks/gspi.h> : #include <soc/gpe.h> : #include <soc/irq.h> : #include <soc/pci_devs.h>
maybe some are not used
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/nvs.h:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... PS37, Line 24: uint16_t
needs <stdint. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/incl... PS37, Line 21: #include <arch/acpi.h> : #include <device/mmio.h> : #include <soc/gpe.h> : #include <soc/iomap.h> : #include <soc/pmc.h>
please check
Done
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 40:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/chip... PS40, Line 548: { : struct bus *nlink = dev->link_list; : while (nlink != NULL) : nlink = nlink->next; : } : why is this block needed?
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 40: Code-Review-1
(4 comments)
just a few more drive-by comments
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... File src/soc/intel/xeon_sp/romstage.c:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... PS37, Line 35: mainboard_config_gpios(); No need to call this, mainboard_config_gpios() is an empty function.
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... PS37, Line 78: mainboard_memory_init_params(mupd); This doesn't do anything, so it should be removed. I suspect it was leftover from Denverton since in that case we need to worry about memory-down configs without SPDs.
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... PS37, Line 85: __weak void mainboard_config_gpios(void) Not needed only called from car_stage_entry() above.
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... PS37, Line 89: __weak void mainboard_memory_init_params(FSPM_UPD *mupd) Similar as above, this can be removed.
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 40:
(7 comments)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 137: size_t hob_size; Iniitialize to zero
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 146: /* Local APICs */ formatting issue?
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 150: hob_size This value will only get assigned if the GUID is found, but can be left uninitialized if not. Since we need to assert (the next line) if it doesn't get set, the variable needs to be initialized to 0 to trigger the assertion in the failure path.
Also, you can join this line and the previous one (the statement will become shorter).
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 160: sizeof(ioapic_ids)/sizeof(int) ARRAY_SIZE(ioapic_ids)
(you'll need include commonlib/helpers.h)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 161: sizeof(gsi_bases)/sizeof(int)) ARRAY_SIZE(gsi_bases)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 172: sizeof(ioapic_ids)/sizeof(int) ARRAY_SIZE(ioapic_ids)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 173: sizeof(gsi_bases)/sizeof(int) ARRAY_SIZE(gsi_bases)
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 40:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... PS40, Line 30: select ARCH_VERSTAGE_X86_32 why do we need verstage?
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... PS40, Line 139: config CPU_BCLK_MHZ : int : default 100 I am not sure this is accurate or applies. Is it used in the patch?
Johnny Lin has uploaded a new patch set (#41) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 49 files changed, 9,104 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/41
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 41:
(11 comments)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 137: size_t hob_size;
Iniitialize to zero
Done
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 146: /* Local APICs */
formatting issue?
Done
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 150: hob_size
This value will only get assigned if the GUID is found, but can be left uninitialized if not. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 160: sizeof(ioapic_ids)/sizeof(int)
ARRAY_SIZE(ioapic_ids) […]
Done
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 161: sizeof(gsi_bases)/sizeof(int))
ARRAY_SIZE(gsi_bases)
Done
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 172: sizeof(ioapic_ids)/sizeof(int)
ARRAY_SIZE(ioapic_ids)
Done
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/acpi... PS40, Line 173: sizeof(gsi_bases)/sizeof(int)
ARRAY_SIZE(gsi_bases)
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... File src/soc/intel/xeon_sp/romstage.c:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... PS37, Line 35: mainboard_config_gpios();
No need to call this, mainboard_config_gpios() is an empty function.
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... PS37, Line 78: mainboard_memory_init_params(mupd);
This doesn't do anything, so it should be removed. […]
It calls into the overridden mainboard_memory_init_params() in mb/ocp/tiogapass/romstage.c which is necessary, it would boot hang if I remove it.
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... PS37, Line 85: __weak void mainboard_config_gpios(void)
Not needed only called from car_stage_entry() above.
Done
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... PS37, Line 89: __weak void mainboard_memory_init_params(FSPM_UPD *mupd)
Similar as above, this can be removed.
Done
Anjaneya "Reddy" Chagam has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 41:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... PS40, Line 30: select ARCH_VERSTAGE_X86_32
why do we need verstage?
Without this, it won't compile. toolchain.inc verstage expects ARCH specific option.
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 41:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... PS40, Line 30: select ARCH_VERSTAGE_X86_32
Without this, it won't compile. toolchain.inc verstage expects ARCH specific option.
ah I see. But we still do not need to compile anything, see my next comment for makefile.inc
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Make... File src/soc/intel/xeon_sp/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Make... PS40, Line 59: verstage-y += soc_util.c : verstage-y += reset.c : verstage-y += spi.c this is probably redudant
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 41:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... PS41, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE, lets not use this. TempRamInit in FSP-T merely adds a write-back MTRR, and CONFIG_CBFS_SIZE doesn't work for this purpose. What we want is to calculate MTRR to cover the whole BIOS region, really.
I think approach in CB:39050 is the better way to do it and it works for me.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 41:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... PS40, Line 30: select ARCH_VERSTAGE_X86_32
ah I see. But we still do not need to compile anything, see my next comment for makefile. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Kcon... PS40, Line 139: config CPU_BCLK_MHZ : int : default 100
I am not sure this is accurate or applies. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Make... File src/soc/intel/xeon_sp/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/Make... PS40, Line 59: verstage-y += soc_util.c : verstage-y += reset.c : verstage-y += spi.c
this is probably redudant
Done
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/40/src/soc/intel/xeon_sp/chip... PS40, Line 548: { : struct bus *nlink = dev->link_list; : while (nlink != NULL) : nlink = nlink->next; : } :
why is this block needed?
Done
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#42).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 49 files changed, 9,086 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/42
Anjaneya "Reddy" Chagam has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 42:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... PS41, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
lets not use this. […]
No it doesn't make sense to set them to zero. Let FSP TempRamInit do its job of setting MTTR. It does hang w/ both SKX FSP and CPX FSP. This is really not desirable to change.
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 42:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... PS41, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
No it doesn't make sense to set them to zero. Let FSP TempRamInit do its job of setting MTTR. […]
I can't agree to that and here is why:
1. We don't want to have dependency on SPI flash size. With the current version of the patch if you put 64mb flash chip in, you would have to adjust both FMD file and CONFIG_CBFS_SIZE.
2. CONFIG_CBFS_SIZE is not used for anything else. In fact in this patch it is used for only that purpose and needs to be dropped. Brevity ftw.
3. if you use fast_spi_cache_bios_region() you will get MTRR set up for you for exactly same BIOS region, and that information would come from IFD, so it is fool proof.
CPX does not hang for me with CodeRegionBase/CodeRegionLength are set to 0. Did you set them to zero or left uninitialized? If it does hang with 0s then it is a FSP bug and needs to be fixed.
Now then, if you absolutely have to use CBFS_SIZE for some reason, here is what can be done to make sense of it. FMD synthax allows for config variable substitution, for example CB:23150 So what you can end up is something like this:
COREBOOT(CBFS)@0x0 ##CBFS_SIZE##
But then again, I really see no good reason to add yet another hardcoded value.
This is slightly off topic, but we should be ditching FSP-T. This value and CONFIG_CPU_MICROCODE_CBFS_LOC/CONFIG_CPU_MICROCODE_CBFS_LEN are similar and only lead to more hardcode across the codebase and only add dependencies.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 42:
(4 comments)
Thanks for contributing server platform code. Given the size of the change, it'll take a while to get through it all, but I'm sure we can get there.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/acpi... PS42, Line 68: #if CONFIG(CONSOLE_CBMEM) use if instead of #if?
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/acpi... PS42, Line 157: bux bus?
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/acpi... PS42, Line 224: idel idle
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/fsp/FspmUpd.h:
PS42: These files probably belong somewhere in src/vendorcode/intel/fsp/fsp2_0/?
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 42:
(57 comments)
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/Kcon... PS42, Line 135: config SMM_TSEG_SIZE : hex : default 0x10000000 : : config SMM_RESERVED_SIZE : hex : default 0x8000000 Is there a particular reason for making these so large? Usually they're a few megabytes (IED wants 4MiB). Since this is kept away from the OS we should probably be conservative.
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/chip... PS41, Line 184: 8_t al tab in between type and variable name
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... File src/soc/intel/xeon_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 45: num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK; num_banks does not appear to be used anywhere?
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 93: */ formatting issue
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 224: */ Did you intend to enable SMIs in this or a follow-up patch?
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 251: /* formatting issue
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 260: /* calls src/cpu/x86/mp_init.c */ formatting issue
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/hob_... File src/soc/intel/xeon_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/hob_... PS21, Line 114: printk(BIOS_DEBUG, "SYSTEM_STATUS: 0x%lx, PLATFORM_DATA: 0x%lx, IIO_RESOURCE_INSTANCE: 0x%lx, STACK_RES: 0x%lx, " : "IIO_DMI_PCIE_INFO: 0x%lx, QPI_IIO_DATA: 0x%lx, QPI_CPU_DATA: 0x%lx, QPI_PEER_DATA: 0x%lx, " : "IIO_PORT_INFO: 0x%lx, UINT64_STRUCT: 0x%lx\n", : sizeof(SYSTEM_STATUS), sizeof(PLATFORM_DATA), sizeof(IIO_RESOURCE_INSTANCE), : sizeof(STACK_RES), sizeof(IIO_DMI_PCIE_INFO), sizeof(QPI_IIO_DATA), : sizeof(QPI_CPU_DATA), sizeof(QPI_PEER_DATA), : sizeof(IIO_PORT_INFO), sizeof(UINT64_STRUCT)); What is this supposed to do? I'd expect to see the value of these fields, not the size.
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... File src/soc/intel/xeon_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 40: return NULL; I don't see where this function is used, so probably better to get rid of it since it doesn't behave as advertised anyway.
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 59: res = fsp_hob_header_to_resource(hob); Since this is dereferenced later on in the function there should probably be a die() or assertion of some kind here.
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 76: size_t hob_size; initialize to 0
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 82: hob, hob_size, sizeof(struct SystemMemoryMapHob), MAX_SOCKET, SAD_RULES); Check the HOB before using it below: assert(hob != NULL && hob_size != 0);
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 104: size_t hob_size; initialize to zero
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/fsp/FspmUpd.h:
PS42:
These files probably belong somewhere in src/vendorcode/intel/fsp/fsp2_0/?
Ideally yes, however this is kind of a pre-release version. Once we have an actual FSP for Xeon SP then it will definitely go in src/vendorcode, but until then we thought it will be best to avoid confusing this with whatever comes out in the (hopefully near) future.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpe.h:
PS42: It seems that nothing in here is actually used, though the header is included by chip.h and uncore.asl. I think we should get rid of this file for now, and use the common Lewisburg PCH code (with CB:35031 applied).
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 44: #pragma pack(1) Does this need to go above the other structs so they get packed as well?
(side note, we usually use __packed in each packed struct's definition to be explicit, but since this seems to come from UEFI code I suppose it's fine to stick with their convention)
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/irq.h:
PS42: Are these #defines used anywhere? I see this headed included by chip.h and uncore.asl. It seems this file was copied from somewhere, so to avoid confusion it might be better to either remove it entirely or remove the #defines to make it a stub that we can add later.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/itss.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 32: #define PCR_ITSS_PIR05 0x314A : #define PCR_ITSS_PIR06 0x314C : #define PCR_ITSS_PIR07 0x314E : #define PCR_ITSS_PIR08 0x3150 : #define PCR_ITSS_PIR09 0x3152 : #define PCR_ITSS_PIR10 0x3154 : #define PCR_ITSS_PIR11 0x3156 : #define PCR_ITSS_PIR12 0x3158 I don't think we have PIR05-12 on this platform.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/p2sb.h:
PS42: Is this file used? Maybe we can get drop it.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 20: #define HPTC_OFFSET 0x60 Prefix with PCH_P2SB?
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 28: #define PCH_PWRM_ACPI_TMR_CTL 0xFC I don't see this in the P2SB config registers, it might be leftover?
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 23: #define PID_PSTH 0x89 What is this supposed to be? The LBG EDS says HSIO strap configuration.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 24: #define PID_GPIOCOM3 0xAC While we're at it, may as well add: PID_GPIOCOM4 0xAB
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 24: needs a tab?
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 29: #define PID_SCS 0xC0 Not on Lewisburg?
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 33: #define PID_SERIALIO 0xCB : #define PID_DMI 0xEF Not on Lewisburg?
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 41: #define PM1_CNT 0x04 For completeness, maybe add SLP_TYP and SLP_EN?
(BTW, I'm just going by the public C620-series datasheet: https://www3.intel.com/content/dam/www/public/us/en/documents/datasheets/c62...)
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 43: #define BM_RLD (1 << 1) Not on Lewisburg
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 48: #define ME_SMI_EN (1 << 30) Add SERIAL_IO_SMI_EN at bit 29
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 50: #define GPIO_UNLOCK_SMI_EN (1 << 27) For completeness, bits 26, 25, 23 should also be in here
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 51: #define INTEL_USB2_EN (1 << 18) : #define LEGACY_USB2_EN (1 << 17) Bits 15-22 are reserved on LBG
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 72: #define SCC_SMI_STS_BIT 25 Add #define for TCO_SMI_EN at bit 23
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 89: #define UPWRC 0x3c : #define UPWRC_WS (1 << 8) : #define UPWRC_WE (1 << 1) : #define UPWRC_SMI (1 << 0) Not on LBG
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 93: #define GPE_CNTL 0x42 This is 0x40 on LBG
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 94: #define SWGPE_CTRL (1 << 1) This is bit 17 on LBG
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 107: #define LAN_WAK_STS (1 << 16) Not on LBG
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 113: #define BATLOW_STS (1 << 10) Not on LBG
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 116: #define TCOSCI_STS (1 << 6) Add IE_SCI_STS at bit 3
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 121: #define LAN_WAK_EN (1 << 16) Not on LBG
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 127: #define BATLOW_EN (1 << 10) Not on LBG
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 128: #define PCI_EXP_EN (1 << 9) Add RI_EN on bit 8
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 133: #define GBLRST_CAUSE0_THERMTRIP (1 << 5) The register offsets for this are defined in pmc.h, maybe this should move into that file? Or just remove it for now if it's unused. (There's some other interesting stuff in those GLBRST registers that we may want to use later on, so we can deal with it then)
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 24: 0x44 It looks like this is intended to be the same as PMC_ACPI_CNT... may as well just define it as such (#define ACTL PMC_ACPI_CNT)
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 42: #define SX_PP_EN (1 << 27) NON_LEG_PCH_MODE at bit 25
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 54: #define ALLOW_L1LOW_OPI_ON (1 << 6) ALLOW_L1LOW_BCLKREQ_ON at bit 5
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 55: #define SMI_LOCK (1 << 4) ESPI_SMI_LOCK at bit 3 PER_SMI_SEL at bit 0 PER_SMI_SEL_MASK 0x3
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 58: #define ACPI_BASE_LOCK (1 << 17) PM_DATA_BAR_DIS at bit 16 PME_B0_S5_DIS at bit 15
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 67: #define HOST_RST_STS (1 << 9) SWSMI_RATESEL_MASK (0x3 << 6) SWSMI_RATESEL_1_5MS (0 << 6) SWSMI_RATESEL_16MS (1 << 6) SWSMI_RATESEL_32MS (2 << 6) SWSMI_RATESEL_64MS (3 << 6)
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 77: #define ETR3 0xac : #define ETR3_CF9LOCK (1 << 31) : #define ETR3_CF9GR (1 << 20) These are defined in pm.h
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 96: #define PMSYNC_TPR_CFG 0xc4 : #define PMSYNC_LOCK (1 << 31) Not on LBG
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 103: #define CIR31C 0x31c : #define XTALSDQDIS (1 << 22) Not on LBG, but we do have CIR324, CIR328, and CIR32C at offsets 0x324, 0x328, and 0x32C
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/smbus.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 35: #define SMBUS_SLAVE_ADDR 0x24 This should be 0x44 for LGB
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/soc_config.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 26: MaxIIO nit: ALLCAPS for #defines
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 38: mmio_resource(dev, index, (uint64_t) ((uint64_t)base >> 10), \ : (uint64_t) ((uint64_t)size >> 10)); \ : LOG_MEM_RESOURCE("mmio", dev, index, (uint64_t) ((uint64_t)base >> 10), \ : (uint64_t) ((uint64_t)size >> 10)); \ Are the casts necessary? An inline (for example add_mmio_resource() in src/soc/intel/braswell/southcluster.c) will allow the compiler to give us a useful error if somebody tries to pass in the wrong type.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/lpc.... File src/soc/intel/xeon_sp/lpc.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/lpc.... PS42, Line 24: static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { Do the ranges mentioned in chapter 7.3 in the LBG EDS (targeting LPC/eSPI) need to be here?
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/rese... File src/soc/intel/xeon_sp/reset.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/rese... PS42, Line 23: die("Reset not implemented!\n"); Perhaps we can use the implementation in src/soc/intel/common/reset.c... but I suppose we can think about that a bit more later.
(marking this comment as resolved)
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/spi.... File src/soc/intel/xeon_sp/spi.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/spi.... PS42, Line 26: case PCH_DEVFN_GSPI0: : return 1; : case PCH_DEVFN_GSPI1: : return 2; Are these used for anything? I don't think we have them on LBG - we only have one SPI bus AFAICT.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 42:
(54 comments)
Thanks for the review. Uploading a new version with majority of comments done, Please review the new version and replies. Will upload another version addressing the rest.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/Kcon... PS42, Line 135: config SMM_TSEG_SIZE : hex : default 0x10000000 : : config SMM_RESERVED_SIZE : hex : default 0x8000000
Is there a particular reason for making these so large? Usually they're a few megabytes (IED wants 4 […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/acpi... PS42, Line 68: #if CONFIG(CONSOLE_CBMEM)
use if instead of #if?
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/acpi... PS42, Line 157: bux
bus?
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/acpi... PS42, Line 224: idel
idle
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/chip... PS41, Line 184: 8_t al
tab in between type and variable name
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... File src/soc/intel/xeon_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 45: num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK;
num_banks does not appear to be used anywhere?
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 93: */
formatting issue
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 224: */
Did you intend to enable SMIs in this or a follow-up patch?
In a follow-up patch.
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 251: /*
formatting issue
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 260: /* calls src/cpu/x86/mp_init.c */
formatting issue
Done
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/hob_... File src/soc/intel/xeon_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/21/src/soc/intel/xeon_sp/hob_... PS21, Line 114: printk(BIOS_DEBUG, "SYSTEM_STATUS: 0x%lx, PLATFORM_DATA: 0x%lx, IIO_RESOURCE_INSTANCE: 0x%lx, STACK_RES: 0x%lx, " : "IIO_DMI_PCIE_INFO: 0x%lx, QPI_IIO_DATA: 0x%lx, QPI_CPU_DATA: 0x%lx, QPI_PEER_DATA: 0x%lx, " : "IIO_PORT_INFO: 0x%lx, UINT64_STRUCT: 0x%lx\n", : sizeof(SYSTEM_STATUS), sizeof(PLATFORM_DATA), sizeof(IIO_RESOURCE_INSTANCE), : sizeof(STACK_RES), sizeof(IIO_DMI_PCIE_INFO), sizeof(QPI_IIO_DATA), : sizeof(QPI_CPU_DATA), sizeof(QPI_PEER_DATA), : sizeof(IIO_PORT_INFO), sizeof(UINT64_STRUCT));
What is this supposed to do? I'd expect to see the value of these fields, not the size.
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... File src/soc/intel/xeon_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 40: return NULL;
I don't see where this function is used, so probably better to get rid of it since it doesn't behave […]
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 59: res = fsp_hob_header_to_resource(hob);
Since this is dereferenced later on in the function there should probably be a die() or assertion of […]
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 76: size_t hob_size;
initialize to 0
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 82: hob, hob_size, sizeof(struct SystemMemoryMapHob), MAX_SOCKET, SAD_RULES);
Check the HOB before using it below: assert(hob != NULL && hob_size != 0);
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/hob_... PS41, Line 104: size_t hob_size;
initialize to zero
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 44: #pragma pack(1)
Does this need to go above the other structs so they get packed as well? […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/itss.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 32: #define PCR_ITSS_PIR05 0x314A : #define PCR_ITSS_PIR06 0x314C : #define PCR_ITSS_PIR07 0x314E : #define PCR_ITSS_PIR08 0x3150 : #define PCR_ITSS_PIR09 0x3152 : #define PCR_ITSS_PIR10 0x3154 : #define PCR_ITSS_PIR11 0x3156 : #define PCR_ITSS_PIR12 0x3158
I don't think we have PIR05-12 on this platform.
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/p2sb.h:
PS42:
Is this file used? Maybe we can get drop it.
Yes, this file is used by src/soc/intel/common/block/p2sb/p2sb.c .
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 20: #define HPTC_OFFSET 0x60
Prefix with PCH_P2SB?
This macro is used in src/soc/intel/common/block/p2sb/p2sb.c to configure HPET.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 28: #define PCH_PWRM_ACPI_TMR_CTL 0xFC
I don't see this in the P2SB config registers, it might be leftover?
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 23: #define PID_PSTH 0x89
What is this supposed to be? The LBG EDS says HSIO strap configuration.
This is for IO Trap PCRs. I am not sure what PSTH stands for, existing codebase expects it, see src/soc/intel/common/block/smm/smitraphandler.c
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 24: #define PID_GPIOCOM3 0xAC
While we're at it, may as well add: […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 24:
needs a tab?
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 29: #define PID_SCS 0xC0
Not on Lewisburg?
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 33: #define PID_SERIALIO 0xCB : #define PID_DMI 0xEF
Not on Lewisburg?
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 41: #define PM1_CNT 0x04
For completeness, maybe add SLP_TYP and SLP_EN? […]
SLP_EN and SLP_TYP are already defined in src/arch/x86/include/arch/acpi.h
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 43: #define BM_RLD (1 << 1)
Not on Lewisburg
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 48: #define ME_SMI_EN (1 << 30)
Add SERIAL_IO_SMI_EN at bit 29
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 50: #define GPIO_UNLOCK_SMI_EN (1 << 27)
For completeness, bits 26, 25, 23 should also be in here
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 51: #define INTEL_USB2_EN (1 << 18) : #define LEGACY_USB2_EN (1 << 17)
Bits 15-22 are reserved on LBG
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 72: #define SCC_SMI_STS_BIT 25
Add #define for TCO_SMI_EN at bit 23
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 89: #define UPWRC 0x3c : #define UPWRC_WS (1 << 8) : #define UPWRC_WE (1 << 1) : #define UPWRC_SMI (1 << 0)
Not on LBG
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 93: #define GPE_CNTL 0x42
This is 0x40 on LBG
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 94: #define SWGPE_CTRL (1 << 1)
This is bit 17 on LBG
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 107: #define LAN_WAK_STS (1 << 16)
Not on LBG
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 113: #define BATLOW_STS (1 << 10)
Not on LBG
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 116: #define TCOSCI_STS (1 << 6)
Add IE_SCI_STS at bit 3
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 121: #define LAN_WAK_EN (1 << 16)
Not on LBG
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 127: #define BATLOW_EN (1 << 10)
Not on LBG
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 128: #define PCI_EXP_EN (1 << 9)
Add RI_EN on bit 8
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 133: #define GBLRST_CAUSE0_THERMTRIP (1 << 5)
The register offsets for this are defined in pmc. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 24: 0x44
It looks like this is intended to be the same as PMC_ACPI_CNT... […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 42: #define SX_PP_EN (1 << 27)
NON_LEG_PCH_MODE at bit 25
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 54: #define ALLOW_L1LOW_OPI_ON (1 << 6)
ALLOW_L1LOW_BCLKREQ_ON at bit 5
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 55: #define SMI_LOCK (1 << 4)
ESPI_SMI_LOCK at bit 3 […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 58: #define ACPI_BASE_LOCK (1 << 17)
PM_DATA_BAR_DIS at bit 16 […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 67: #define HOST_RST_STS (1 << 9)
SWSMI_RATESEL_MASK (0x3 << 6) […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 77: #define ETR3 0xac : #define ETR3_CF9LOCK (1 << 31) : #define ETR3_CF9GR (1 << 20)
These are defined in pm. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 96: #define PMSYNC_TPR_CFG 0xc4 : #define PMSYNC_LOCK (1 << 31)
Not on LBG
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 103: #define CIR31C 0x31c : #define XTALSDQDIS (1 << 22)
Not on LBG, but we do have CIR324, CIR328, and CIR32C at offsets 0x324, 0x328, and 0x32C
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/smbus.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 35: #define SMBUS_SLAVE_ADDR 0x24
This should be 0x44 for LGB
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/soc_config.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 26: MaxIIO
nit: ALLCAPS for #defines
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 38: mmio_resource(dev, index, (uint64_t) ((uint64_t)base >> 10), \ : (uint64_t) ((uint64_t)size >> 10)); \ : LOG_MEM_RESOURCE("mmio", dev, index, (uint64_t) ((uint64_t)base >> 10), \ : (uint64_t) ((uint64_t)size >> 10)); \
Are the casts necessary? An inline (for example add_mmio_resource() in src/soc/intel/braswell/southc […]
Done
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#43).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/fsp/FspUpd.h A src/soc/intel/xeon_sp/include/fsp/FspmUpd.h A src/soc/intel/xeon_sp/include/fsp/FspsUpd.h A src/soc/intel/xeon_sp/include/fsp/FsptUpd.h A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpe.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/hob_iiouds.h A src/soc/intel/xeon_sp/include/soc/hob_memmap.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 49 files changed, 8,985 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/43
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 43:
(7 comments)
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... File src/soc/intel/xeon_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/cpu.... PS41, Line 224: */
In a follow-up patch.
Ack
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/irq.h:
PS42:
Are these #defines used anywhere? I see this headed included by chip.h and uncore.asl. […]
Thanks for cleaning out the unused #defines. We can add them back later as needed.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/p2sb.h:
PS42:
Yes, this file is used by src/soc/intel/common/block/p2sb/p2sb.c .
Ack
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 20: #define HPTC_OFFSET 0x60
This macro is used in src/soc/intel/common/block/p2sb/p2sb.c to configure HPET.
Ack
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 23: #define PID_PSTH 0x89
This is for IO Trap PCRs. […]
Thanks for pointing that out, I'll check into it in more detail and submit a correction in a follow-up if needed.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... PS42, Line 41: #define PM1_CNT 0x04
SLP_EN and SLP_TYP are already defined in src/arch/x86/include/arch/acpi. […]
Ack
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... File src/soc/intel/xeon_sp/romstage.c:
https://review.coreboot.org/c/coreboot/+/38548/37/src/soc/intel/xeon_sp/roms... PS37, Line 78: mainboard_memory_init_params(mupd);
It calls into the overridden mainboard_memory_init_params() in mb/ocp/tiogapass/romstage. […]
Oops, I must have missed that. Thanks!
Anjaneya "Reddy" Chagam has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 43:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... PS41, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
I can't agree to that and here is why: […]
No disconnect on your recommendation!! There is regression with this change - hangs post silicon init phase and I prefer to focus on this after initial merge.
This whole thing will be moot once we move away from using FspTempRamInit which needs to be the focus.
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#44).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 42 files changed, 7,448 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/44
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 44:
(4 comments)
Thanks for the review. Appreciate it!
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/fsp/FspmUpd.h:
PS42:
Ideally yes, however this is kind of a pre-release version. […]
In addition to FSP UPD header files,the FSP HOB header files are also moved to src/vendorcode/intel/fsp/fsp2_0. In the commit message, I stated that these header files are from a FSP engineering build.
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpe.h:
PS42:
It seems that nothing in here is actually used, though the header is included by chip.h and uncore. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/lpc.... File src/soc/intel/xeon_sp/lpc.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/lpc.... PS42, Line 24: static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
Do the ranges mentioned in chapter 7. […]
PCH initialization is done by FSP, so we don't do anything here
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/spi.... File src/soc/intel/xeon_sp/spi.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/spi.... PS42, Line 26: case PCH_DEVFN_GSPI0: : return 1; : case PCH_DEVFN_GSPI1: : return 2;
Are these used for anything? I don't think we have them on LBG - we only have one SPI bus AFAICT.
Done
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 44:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/lpc.... File src/soc/intel/xeon_sp/lpc.c:
https://review.coreboot.org/c/coreboot/+/38548/42/src/soc/intel/xeon_sp/lpc.... PS42, Line 24: static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
PCH initialization is done by FSP, so we don't do anything here
Forgot to resolve this.
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 44:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38548/44/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/44/src/soc/intel/xeon_sp/soc_... PS44, Line 375: 127 hm this can't be right. Why other bus numbers are power of two and below it is 1 less?
https://review.coreboot.org/c/coreboot/+/38548/44/src/soc/intel/xeon_sp/soc_... PS44, Line 361: switch (maxbusno) { : case 0: : printk(BIOS_DEBUG, "Max Bus Number 2048 (2GB MMCFG Range)\n"); : break; : case 1: : printk(BIOS_DEBUG, "Max Bus Number 1048 (1GB MMCFG range)\n"); : break; : case 2: : printk(BIOS_DEBUG, "Max Bus Number 512 (512MB MMCFG range)\n"); : break; : case 4: : printk(BIOS_DEBUG, "Max Bus Number 256 (256MB MMCFG range)\n"); : break; : case 5: : printk(BIOS_DEBUG, "Max Bus Number 127 (128MB MMCFG range)\n"); : break; : case 6: : printk(BIOS_DEBUG, "Max Bus Number 63 (64MB MMCFG range)\n"); : break; : default: : printk(BIOS_DEBUG, "Invalid Max Bus Number 0x%x\n", maxbusno); : break; : } up to you, but this switch statement can be colapsed into:
printk(BIOS_DEBUG, "Max bus number %u (%u MB MMCFG Range)\n", (1 << (11 - maxbusno)) - 1, (1 << (11 - maxbusno)));
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 44:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... PS41, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
No disconnect on your recommendation!! There is regression with this change - hangs post silicon ini […]
So this change is causing a regression? Why land something that is broken? There's also only so much mmio space for memory mapped spi flash. The spi flash size can definitely exceed the available mmio space. I agree with Andrey that CB:39050 is the correct way to achieve the desired results. Perhaps providing more details on the 'regression' would help in evaluating correct path forward.
Anjaneya "Reddy" Chagam has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 44:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... PS41, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
So this change is causing a regression? Why land something that is broken? There's also only so much […]
I am going to push this change and move on!! Issue happens sporadically on 2S Tioga Pass Server where PCU mail box command times out. This will take time to debug considering this is happening very late in the boot flow (post silicon init).
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#45).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 42 files changed, 6,899 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/45
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 45:
(3 comments)
Thanks for the review!
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... PS41, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
I am going to push this change and move on!! Issue happens sporadically on 2S Tioga Pass Server wher […]
We are going to figure out why this preferred method degrades boot stability. A follow-up patch will be made accordingly.
https://review.coreboot.org/c/coreboot/+/38548/44/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/44/src/soc/intel/xeon_sp/soc_... PS44, Line 375: 127
hm this can't be right. […]
This function is for debug purpose. It is removed.
https://review.coreboot.org/c/coreboot/+/38548/44/src/soc/intel/xeon_sp/soc_... PS44, Line 361: switch (maxbusno) { : case 0: : printk(BIOS_DEBUG, "Max Bus Number 2048 (2GB MMCFG Range)\n"); : break; : case 1: : printk(BIOS_DEBUG, "Max Bus Number 1048 (1GB MMCFG range)\n"); : break; : case 2: : printk(BIOS_DEBUG, "Max Bus Number 512 (512MB MMCFG range)\n"); : break; : case 4: : printk(BIOS_DEBUG, "Max Bus Number 256 (256MB MMCFG range)\n"); : break; : case 5: : printk(BIOS_DEBUG, "Max Bus Number 127 (128MB MMCFG range)\n"); : break; : case 6: : printk(BIOS_DEBUG, "Max Bus Number 63 (64MB MMCFG range)\n"); : break; : default: : printk(BIOS_DEBUG, "Invalid Max Bus Number 0x%x\n", maxbusno); : break; : }
up to you, but this switch statement can be colapsed into: […]
This function is for debug purpose. It is removed.
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 45: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/45/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/38548/45/src/soc/intel/xeon_sp/incl... PS45, Line 25: void I don't think mainboard_config_gpios() is called directly outside of the mainboard's own romstage.c file, so you should not need to define it here.
However, if for some reason you do need it here then the argument needs to be `FSPM_UPD *mupd` to work with the declaration in the mainboard's romstage.c (in the follow-up patch).
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 45:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/45/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/45/src/soc/intel/xeon_sp/Kcon... PS45, Line 87: string In order fort his to show up in menuconfig, this needs to have a value. So perhaps: string "Location of FSP binary"
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 45:
(2 comments)
Thanks for the review!
https://review.coreboot.org/c/coreboot/+/38548/45/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/45/src/soc/intel/xeon_sp/Kcon... PS45, Line 87: string
In order fort his to show up in menuconfig, this needs to have a value. So perhaps: […]
Done
https://review.coreboot.org/c/coreboot/+/38548/45/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/38548/45/src/soc/intel/xeon_sp/incl... PS45, Line 25: void
I don't think mainboard_config_gpios() is called directly outside of the mainboard's own romstage. […]
Done
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#46).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 42 files changed, 6,898 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/46
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#47).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 42 files changed, 6,898 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/47
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 47:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38548/46/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/46/src/soc/intel/xeon_sp/chip... PS46, Line 432: struct iiostack_resource stack_info; let's zero-initialize this without calling memset:
struct iiostack_resource stack_info = { 0 };
https://review.coreboot.org/c/coreboot/+/38548/46/src/soc/intel/xeon_sp/chip... PS46, Line 446: stack_info.sres it looks like we are malloc()'ing stack_info.sres in get_iiostack_info() called above, and then freeing it here. It sounds like we can drop dynamic memory management here.
I think this can be simplified like this:
struct iiostack_resource { size_t no_of_stacks; STACK_RES res[MAX_IIO_STACK]; };
struct iiostack_resource stack_info = {0}; get_iiostack_info(&stack_info); // do whatever work is needed
This way you can get rid of malloc(), free() and memset()
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 47:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... PS47, Line 208: /* Mark FSP region */ : base_kb = (range_entry_base(&fsp_mem) >> 10); : size_kb = (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1) >> 10; : LOG_MEM_RESOURCE("mmio_fsp", dev, index, base_kb, size_kb); : mmio_resource(dev, index++, base_kb, size_kb); : you don't need to explicitly mark FSP's region. This is done automagically in fsp_memory_init() as part of cbmem initialization()
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... PS47, Line 214: /* Mark coreboot region as reserved */ : base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - : range_entry_base(&fsp_mem) + 1)) >> 10; : size_kb = (mc_values[TSEG_BASE_REG] - (base_kb << 10)) >> 10; : LOG_MEM_RESOURCE("mmio_coreboot", dev, index, base_kb, size_kb); : mmio_resource(dev, index++, base_kb, size_kb); I do not understand what is the "coreboot region". Could you please explain what is being added as MMIO resource?
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... PS47, Line 225: mmio_resource(dev, index++, base_kb, size_kb); I think that we mark SMM as reserved resource, not MMIO.
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... PS47, Line 232: mmio_resource(dev, index++, base_kb, size_kb); I believe this is not MMIO as well
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 47:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 18: #include <assert.h> : #include <arch/acpi.h> : #include <arch/cpu.h> : #include <arch/acpigen.h> : #include <arch/ioapic.h> : #include <arch/smp/mpspec.h> : #include <bootstate.h> : #include <string.h> : #include <cf9_reset.h> : #include <cpu/intel/turbo.h> : #include <cpu/x86/msr.h> : #include <cpu/x86/smm.h> : #include <intelblocks/acpi.h> : #include <intelblocks/msr.h> : #include <intelblocks/pmclib.h> : #include <device/pci.h> : #include <cbmem.h> : #include <soc/acpi.h> : #include <soc/cpu.h> : #include <soc/soc_util.h> : #include <soc/pm.h> : #include <soc/pmc.h> : #include <soc/pci_devs.h> : #include <soc/soc_util.h> : #include <soc/hob_iiouds.h> : #include <soc/hob_memmap.h> : #include "chip.h"
Done
Done
https://review.coreboot.org/c/coreboot/+/38548/10/src/soc/intel/skylake_sp/a... PS10, Line 240:
The code I added/updated does not use Processor, actually with this patchset, there is no processor/ […]
Done
https://review.coreboot.org/c/coreboot/+/38548/14/src/soc/intel/skylake_sp/a... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/14/src/soc/intel/skylake_sp/a... PS14, Line 25: msr
Done
Done
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 47:
(6 comments)
Thanks for the comments.
https://review.coreboot.org/c/coreboot/+/38548/46/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/46/src/soc/intel/xeon_sp/chip... PS46, Line 432: struct iiostack_resource stack_info;
let's zero-initialize this without calling memset: […]
Done
https://review.coreboot.org/c/coreboot/+/38548/46/src/soc/intel/xeon_sp/chip... PS46, Line 446: stack_info.sres
it looks like we are malloc()'ing stack_info. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... PS47, Line 208: /* Mark FSP region */ : base_kb = (range_entry_base(&fsp_mem) >> 10); : size_kb = (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1) >> 10; : LOG_MEM_RESOURCE("mmio_fsp", dev, index, base_kb, size_kb); : mmio_resource(dev, index++, base_kb, size_kb); :
you don't need to explicitly mark FSP's region. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... PS47, Line 214: /* Mark coreboot region as reserved */ : base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - : range_entry_base(&fsp_mem) + 1)) >> 10; : size_kb = (mc_values[TSEG_BASE_REG] - (base_kb << 10)) >> 10; : LOG_MEM_RESOURCE("mmio_coreboot", dev, index, base_kb, size_kb); : mmio_resource(dev, index++, base_kb, size_kb);
I do not understand what is the "coreboot region". […]
Done
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... PS47, Line 225: mmio_resource(dev, index++, base_kb, size_kb);
I think that we mark SMM as reserved resource, not MMIO.
Done
https://review.coreboot.org/c/coreboot/+/38548/47/src/soc/intel/xeon_sp/unco... PS47, Line 232: mmio_resource(dev, index++, base_kb, size_kb);
I believe this is not MMIO as well
Done
Hello Patrick Rudolph, HAOUAS Elyes, Angel Pons, Johnny Lin, David Hendricks, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#48).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 42 files changed, 6,874 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/48
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 50: Code-Review-1
(13 comments)
Almost there!
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi/pci_irq.asl:
PS50: please indent with tabs
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi/uncore.asl:
PS50: please indent uniformly with tabs
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 165: npr == 0 npr == NULL
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 166: assign_resource_to_stack add_res_to_stack()
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 197: bool first = 1 int first? Or if you prefer to keep it as a bool, use true/false instead of 1/0.
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 284: continue; Join lines 281-283 so that the parens terminate after the condition. Right now it looks like `continue` is left out of the if-statement (I had to open up my editor to be sure there wasn't a bug...).
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 317: 0 NULL
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 512: 0 NULL
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 516: 0 NULL
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 518: struct bus nit: use the object's size in case the type ever changes, i.e. sizeof(*iiostack_bus)
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 519: struct bus ditto
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/cpu.... File src/soc/intel/xeon_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/cpu.... PS50, Line 92: * nit: indentation
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/cpu.... PS50, Line 188: nit: extra line
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 50:
(24 comments)
Great job, we are definitely getting there. I think we are almost there. I wish we had the patch split into smaller chunks. This way we would need less rounds.
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/Kcon... PS50, Line 59: select SOC_INTEL_COMMON_BLOCK_P2SB we are not using this. We could use it, if PCH id are added into block/p2sb/p2sb.c.
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/Kcon... PS50, Line 60: SOC_INTEL_COMMON_BLOCK_ITSS I do not see the code use ITSS
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 516: acpi_create_serialio_ssdt(ssdt2); : if (ssdt2->length) { : current += ssdt2->length; : acpi_add_table(rsdp, ssdt2); : printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2, : ssdt2->length); : current = (ALIGN(current, 16)); : } else { : ssdt2 = NULL; : printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); : } this code does nothing, doesn't it? so lets drop it
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 720: uint16_t hpet_capid = *(volatile u16 *)(unsigned int)(HPET_BASE_ADDRESS); replace with read16()
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 721: uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count same
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 726: *((volatile uint32_t *)(uint32_t)(HPET_BASE_ADDRESS + 0x100)) read32()
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 760: uint64_t vtd_mmio_cap = *(volatile uint64_t *)(unsigned int)(vtd_base + read64()
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 1041: __weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} not needed
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... PS41, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
We are going to figure out why this preferred method degrades boot stability. […]
I just realized we have CONFIG_ROM_SIZE for that. Since there is regression we may want to use this instead:
.CodeRegionBase = 0xffffffff - CONFIG_ROM_SIZE + 1; .CodeRegionLength = CONFIG_ROM_SIZE;
this may not be the perfect way though, because we cover whole flash. And I believe only BIOS region is memory mapped. This is just a suggestion in case we may have hard time fixing the hang issue that was mentioned.
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 22: /// Use below for functions from PCH GPIO Lib which : /// require GpioGroup as argument what PCH GPIO Lib? please remove this
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 39: /// same here
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 40: #define UART_BASE_SIZE 0x1000 : #define UART_BASE_0_ADDRESS 0xfe030000 : /* Both UART BAR 0 and 1 are 4KB in size */ : #define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * UART_BASE_SIZE * (x))) : #define UART_BASE(x) UART_BASE_0_ADDR(x) there is no memory-mapped UART on this platform
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/itss.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 20: #define GPIO_IRQ_START 50 : #define GPIO_IRQ_END ITSS_MAX_IRQ : : #define ITSS_MAX_IRQ 119 : #define IRQS_PER_IPC 32 : #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) : : #define PCR_ITSS_PIR00 0x3140 : #define PCR_ITSS_PIR01 0x3142 : #define PCR_ITSS_PIR02 0x3144 : #define PCR_ITSS_PIR03 0x3146 : : #define PCH_PCR_ITSS_IPC0 0x3200 ///< Interrupt Polarity Control 0 : #define PCH_PCR_ITSS_IPC1 0x3204 ///< Interrupt Polarity Control 1 : #define PCH_PCR_ITSS_IPC2 0x3208 ///< Interrupt Polarity Control 2 : #define PCH_PCR_ITSS_IPC3 0x320C we are not using these values anywhere. Since we are not using that, lets drop the whole file?
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 33: #define PID_SERIALIO 0xCB I don't see serialio in C620 datasheet. What data sheet this is from? (I couldn't find c621 datasheet only c620)
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 36: define PCH_PCR_ADDRESS(Pid, Offset) \ : (P2SB_BAR | ((uint8_t)(Pid) << 16) | (uint16_t)(Offset)) this macro is not used and should be dropped
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/soc_config.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 20: #define IIO_UPLINK_PORT_INDEX 5 : #define MAX_TAD_RULES 20 : #define MAX_TAD_WAYS 3 : #define MAX_DPC 2 : #define MAX_SPD_BYTES 512 these are not used anywhere in the patch. Lets just drop the whole file
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... File src/soc/intel/xeon_sp/lpc.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... PS50, Line 57: 0xfd00 why this index? doesn't look like it has to be this value
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... PS50, Line 62: res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); : res->base = FIRMWARE_BASE_ADDRESS; : res->size = FIRMWARE_BASE_SIZE; /* 16 MB for flash */ lets avoid hardcoding flash size. chip code should not depend on board-specific bits. also: why are we adding BIOS region as a resource?
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... PS50, Line 67: LOG_MEM_RESOURCE("[MEM] subtractive_res", dev, io_index-1, I think it may be good idea to refactor LOG_MEM_RESOURCE macro to take dev and res. This way you can drop this "io_index-1"
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... PS50, Line 71: res = new_resource(dev, 0xda); : res->base = P2SB_BAR; : res->size = P2SB_SIZE; : res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | : IORESOURCE_ASSIGNED; : LOG_MEM_RESOURCE("P2SB PCR config space BAR", dev, 0xda, : (res->base >> 10), (res->size >> 10)); so this region [P2SB_BAR;P2SB_BAR+P2SB_SIZE] already covers region [PCH_BASE_ADDRESS; PCH_BASE_ADDRESS+PCH_BASE_SIZE]. So the latter one is redundant and should not be removed. However, we already have common code for that. Please add p2sb pci device ids into block/p2sb/p2sb.c and we can drop this code as well.
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/soc_... PS50, Line 27: #include <intelblocks/itss.h> we are not using this
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/soc_... PS50, Line 31: #include <soc/itss.h> neither this
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/unco... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/unco... PS50, Line 257: 0xa0000 VGA_BASE_ADDRESS
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/unco... PS50, Line 258: (0xc0000 - 0xa0000) >> 10; VGA_BASE_SIZE
David Hendricks has uploaded a new patch set (#51) to the change originally created by Jonathan Zhang. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpio_fsp.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/itss.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/p2sb.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/smbus.h A src/soc/intel/xeon_sp/include/soc/soc_config.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 42 files changed, 6,874 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/51
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 51:
(36 comments)
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/Kcon... PS50, Line 59: select SOC_INTEL_COMMON_BLOCK_P2SB
we are not using this. We could use it, if PCH id are added into block/p2sb/p2sb.c.
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/Kcon... PS50, Line 60: SOC_INTEL_COMMON_BLOCK_ITSS
I do not see the code use ITSS
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 516: acpi_create_serialio_ssdt(ssdt2); : if (ssdt2->length) { : current += ssdt2->length; : acpi_add_table(rsdp, ssdt2); : printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2, : ssdt2->length); : current = (ALIGN(current, 16)); : } else { : ssdt2 = NULL; : printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); : }
this code does nothing, doesn't it? so lets drop it
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 720: uint16_t hpet_capid = *(volatile u16 *)(unsigned int)(HPET_BASE_ADDRESS);
replace with read16()
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 721: uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count
same
This can not be replaced with read16()
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 726: *((volatile uint32_t *)(uint32_t)(HPET_BASE_ADDRESS + 0x100))
read32()
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 760: uint64_t vtd_mmio_cap = *(volatile uint64_t *)(unsigned int)(vtd_base +
read64()
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... PS50, Line 1041: __weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {}
not needed
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi/pci_irq.asl:
PS50:
please indent with tabs
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/acpi... File src/soc/intel/xeon_sp/acpi/uncore.asl:
PS50:
please indent uniformly with tabs
Done
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... File src/soc/intel/xeon_sp/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... PS41, Line 33: .CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE), : .CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
I just realized we have CONFIG_ROM_SIZE for that. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 165: npr == 0
npr == NULL
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 166: assign_resource_to_stack
add_res_to_stack()
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 197: bool first = 1
int first? Or if you prefer to keep it as a bool, use true/false instead of 1/0.
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 284: continue;
Join lines 281-283 so that the parens terminate after the condition. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 317: 0
NULL
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 516: 0
NULL
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 518: struct bus
nit: use the object's size in case the type ever changes, i.e. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 519: struct bus
ditto
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/cpu.... File src/soc/intel/xeon_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/cpu.... PS50, Line 92: *
nit: indentation
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/cpu.... PS50, Line 188:
nit: extra line
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 22: /// Use below for functions from PCH GPIO Lib which : /// require GpioGroup as argument
what PCH GPIO Lib? please remove this
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 39: ///
same here
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 40: #define UART_BASE_SIZE 0x1000 : #define UART_BASE_0_ADDRESS 0xfe030000 : /* Both UART BAR 0 and 1 are 4KB in size */ : #define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * UART_BASE_SIZE * (x))) : #define UART_BASE(x) UART_BASE_0_ADDR(x)
there is no memory-mapped UART on this platform
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/itss.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 20: #define GPIO_IRQ_START 50 : #define GPIO_IRQ_END ITSS_MAX_IRQ : : #define ITSS_MAX_IRQ 119 : #define IRQS_PER_IPC 32 : #define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC) : : #define PCR_ITSS_PIR00 0x3140 : #define PCR_ITSS_PIR01 0x3142 : #define PCR_ITSS_PIR02 0x3144 : #define PCR_ITSS_PIR03 0x3146 : : #define PCH_PCR_ITSS_IPC0 0x3200 ///< Interrupt Polarity Control 0 : #define PCH_PCR_ITSS_IPC1 0x3204 ///< Interrupt Polarity Control 1 : #define PCH_PCR_ITSS_IPC2 0x3208 ///< Interrupt Polarity Control 2 : #define PCH_PCR_ITSS_IPC3 0x320C
we are not using these values anywhere. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 33: #define PID_SERIALIO 0xCB
I don't see serialio in C620 datasheet. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 36: define PCH_PCR_ADDRESS(Pid, Offset) \ : (P2SB_BAR | ((uint8_t)(Pid) << 16) | (uint16_t)(Offset))
this macro is not used and should be dropped
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... File src/soc/intel/xeon_sp/include/soc/soc_config.h:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/incl... PS50, Line 20: #define IIO_UPLINK_PORT_INDEX 5 : #define MAX_TAD_RULES 20 : #define MAX_TAD_WAYS 3 : #define MAX_DPC 2 : #define MAX_SPD_BYTES 512
these are not used anywhere in the patch. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... File src/soc/intel/xeon_sp/lpc.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... PS50, Line 57: 0xfd00
why this index? doesn't look like it has to be this value
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... PS50, Line 62: res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); : res->base = FIRMWARE_BASE_ADDRESS; : res->size = FIRMWARE_BASE_SIZE; /* 16 MB for flash */
lets avoid hardcoding flash size. chip code should not depend on board-specific bits. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... PS50, Line 67: LOG_MEM_RESOURCE("[MEM] subtractive_res", dev, io_index-1,
I think it may be good idea to refactor LOG_MEM_RESOURCE macro to take dev and res. […]
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/lpc.... PS50, Line 71: res = new_resource(dev, 0xda); : res->base = P2SB_BAR; : res->size = P2SB_SIZE; : res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | : IORESOURCE_ASSIGNED; : LOG_MEM_RESOURCE("P2SB PCR config space BAR", dev, 0xda, : (res->base >> 10), (res->size >> 10));
so this region [P2SB_BAR;P2SB_BAR+P2SB_SIZE] already covers region [PCH_BASE_ADDRESS; PCH_BASE_ADDRE […]
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/soc_... File src/soc/intel/xeon_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/soc_... PS50, Line 27: #include <intelblocks/itss.h>
we are not using this
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/soc_... PS50, Line 31: #include <soc/itss.h>
neither this
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/unco... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/unco... PS50, Line 257: 0xa0000
VGA_BASE_ADDRESS
Done
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/unco... PS50, Line 258: (0xc0000 - 0xa0000) >> 10;
VGA_BASE_SIZE
Done
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 51:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/50/src/soc/intel/xeon_sp/chip... PS50, Line 512: 0
NULL
BusBase is a field of uint8_t.
Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, Johnny Lin, David Hendricks, Angel Pons, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#52).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 36 files changed, 5,497 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/52
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 52:
(619 comments)
Patch Set 3:
(169 comments)
Just clearing out some stale lint comments - I think I got all the ones up thru (including) to PS4
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 770: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 771: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 773: u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 838: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 993: acpigen_emit_byte(type_flags); // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1012: const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1014: snprintf(rtname, sizeof(rtname), "RT%02x", (socket*MAX_IIO_STACK)+stack);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1026: if (socket == 0 && stack == 0) { // additional io resources on socket 0 bus 0
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1031: acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1032: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1033: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1034: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1042: if (socket == 0 && stack == 0) { // additional mem32 resources on socket 0 bus 0
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1044: (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_BASE_SIZE);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ac... PS1, Line 1046: (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, SPI_BASE_SIZE);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 182: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 192: socket, stack, ioapic_id, ri->IoApicBase + 0x1000, gsi_base);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 193: current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 668: PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 685: current += acpi_create_dmar_ds_pci(current, bus, CBDMA_DEV_NUM, cbdma_func_id);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 695: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 696: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 712: current += acpi_create_dmar_ds_pci(current, bus, VMD_DEV_NUM, VMD_FUNC_NUM);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 723: (*((volatile u32 *)(u32)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { // BIT 15
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 751: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 754: u64 vtd_mmio_cap = *(volatile u64 *)(unsigned int) (vtd_base + VTD_EXT_CAP_LOW);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 756: __func__, socket, stack, bus, vtd_base, vtd_mmio_cap);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 770: u32 dev = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Device;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 771: u32 func = hob->PlatformData.IIO_resource[socket].PcieInfo.PortInfo[p].Function;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 773: u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 838: hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 993: acpigen_emit_byte(type_flags); // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1012: const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1014: snprintf(rtname, sizeof(rtname), "RT%02x", (socket*MAX_IIO_STACK)+stack);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1026: if (socket == 0 && stack == 0) { // additional io resources on socket 0 bus 0
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1031: acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1032: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1033: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1034: acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1042: if (socket == 0 && stack == 0) { // additional mem32 resources on socket 0 bus 0
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1044: (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_BASE_SIZE);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ac... PS2, Line 1046: (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, SPI_BASE_SIZE);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1054: (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, VGA_BASE_SIZE);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ac... PS3, Line 1056: (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, SPI_BASE_SIZE);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 385: res->base, res->limit, (bridge ? resource_type(res) : ""));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 391: } else {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 392: /* update bridge range from child bridge range */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 393: if (res->base < bridge->base)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 395: if (res->limit > bridge->limit)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 398: bridge->size = (bridge->limit - bridge->base + 1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH))
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ch... PS1, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 385: res->base, res->limit, (bridge ? resource_type(res) : ""));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 391: } else {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 392: /* update bridge range from child bridge range */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 393: if (res->base < bridge->base)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 395: if (res->limit > bridge->limit)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 398: bridge->size = (bridge->limit - bridge->base + 1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH))
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ch... PS2, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 147: res->align, res->gran, res->limit, res->flags, resource_type(res),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 152: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 170: (res->flags & IORESOURCE_PREFETCH) ? " prefetchable " : " non-prefetchable",
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 314: if (first) { /* this bridge doesn't have any resources, will set it to default window */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 385: res->base, res->limit, (bridge ? resource_type(res) : ""));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 391: } else {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 392: /* update bridge range from child bridge range */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 393: if (res->base < bridge->base)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 395: if (res->limit > bridge->limit)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 398: bridge->size = (bridge->limit - bridge->base + 1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 412: flags[0] = bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 413: if ((bridge->flags & IORESOURCE_MEM) && (bridge->flags & IORESOURCE_PREFETCH))
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 437: ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PCI64
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 540: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 601: if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ch... PS3, Line 621: printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... File src/soc/intel/skylake_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 387: if (!(bridge->flags & IORESOURCE_ASSIGNED)) { /* for 1st time update, overlading IORESOURCE_ASSIGNED */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 391: } else {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 392: /* update bridge range from child bridge range */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 393: if (res->base < bridge->base)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 395: if (res->limit > bridge->limit)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 398: bridge->size = (bridge->limit - bridge->base + 1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 400: __func__, resource_type(res), bridge->base, bridge->size, bridge->limit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 533: link->secondary, stack->BusBase, stack->BusLimit, stack->PciResourceIoBase,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ch... PS4, Line 584: .acpi_fill_ssdt_generator = generate_cpu_entries, /* defined in src/soc/intel/common/block/acpi/acpi.c */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... PS1, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... PS1, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/cp... PS1, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... PS2, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... PS2, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/cp... PS2, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... PS3, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... PS3, Line 182: {X86_VENDOR_INTEL, CPUID_SKYLAKESP_A0_A1}, /* Skylake-SP A0/A1 CPUID 0x506f0*/
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/cp... PS3, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... File src/soc/intel/skylake_sp/cpu.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... PS4, Line 168: /* MSR_IA32_HWP_REQUEST read results in halt!! FSP clears Energy_Performance_Preference to 0 (default is 0x80) */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/cp... PS4, Line 300: /* This gets used in cpu device callback. Other than cpu 0, rest of the CPU devices do not have
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/ho... PS1, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/ho... PS2, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 97: e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 182: printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", hob->PlatformData.IIO_resource[s].SocketID);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 183: printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", hob->PlatformData.IIO_resource[s].BusBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 184: printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", hob->PlatformData.IIO_resource[s].BusLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 208: printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", ri->PciResourceIoBase);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 209: printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", ri->PciResourceIoLimit);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 226: p, hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Device,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 227: hob->PlatformData.IIO_resource[s].PcieInfo.PortInfo[p].Function);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/ho... PS3, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... File src/soc/intel/skylake_sp/hob_display.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/ho... PS4, Line 234: printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", socket, stack,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 55: UINT8 SocketFirstBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 56: UINT8 SocketLastBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 57: UINT8 segmentSocket;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 58: UINT8 PcieSegment;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 60: UINT8 stackPresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 61: UINT8 StackBus[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 62: UINT8 M2PciePresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 63: UINT8 TotM3Kti;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 84: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 85: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 88: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 89: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 90: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 91: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 100: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 101: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 104: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 105: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 106: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 107: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 108: STACK_RES StackRes[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 55: UINT8 SocketFirstBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 56: UINT8 SocketLastBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 57: UINT8 segmentSocket;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 58: UINT8 PcieSegment;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 60: UINT8 stackPresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 61: UINT8 StackBus[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 62: UINT8 M2PciePresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 63: UINT8 TotM3Kti;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 84: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 85: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 88: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 89: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 90: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 91: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 100: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 101: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 104: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 105: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 106: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 107: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 108: STACK_RES StackRes[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 55: UINT8 SocketFirstBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 56: UINT8 SocketLastBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 57: UINT8 segmentSocket;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 58: UINT8 PcieSegment;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 60: UINT8 stackPresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 61: UINT8 StackBus[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 62: UINT8 M2PciePresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 63: UINT8 TotM3Kti;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 84: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 85: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 88: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 89: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 90: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 91: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 100: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 101: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 104: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 105: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 106: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 107: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 108: STACK_RES StackRes[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_iiouds.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 47: UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 55: UINT8 SocketFirstBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 56: UINT8 SocketLastBus;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 57: UINT8 segmentSocket;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 58: UINT8 PcieSegment;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 60: UINT8 stackPresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 61: UINT8 StackBus[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 62: UINT8 M2PciePresentBitmap;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 63: UINT8 TotM3Kti;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 67: QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 73: QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 84: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 85: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 88: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 89: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 90: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 91: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 100: UINT16 PciResourceIoBase;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 101: UINT16 PciResourceIoLimit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 104: UINT32 PciResourceMem32Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 105: UINT32 PciResourceMem32Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 106: UINT64 PciResourceMem64Base;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 107: UINT64 PciResourceMem64Limit;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 108: STACK_RES StackRes[MAX_IIO_STACK];
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 131: UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 140: UINT64 softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 141: BOOLEAN Simics; // TRUE - Simics Environtment; FALSE - H\w
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 146: UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 147: UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 148: UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 150: UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 160: UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 161: UINT32 FusedCores[MAX_SOCKET]; ///< Fused Core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 162: UINT32 ActiveCores[MAX_SOCKET];// Current activated core Mask in the package
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 163: UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 164: UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 165: UINT8 CurrentCoreToBusRatio; // Current system Core to Bus Ratio
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 166: UINT32 IntelSpeedSelectCapable; // ISS Capable (system level) Bit[7:0] and current Config TDP Level Bit[15:8]
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 167: UINT32 IssConfigTdpLevelInfo; // get B2P CONFIG_TDP_GET_LEVELS_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 168: UINT32 IssConfigTdpTdpInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_TDP_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 169: UINT32 IssConfigTdpPowerInfo[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_POWER_INFO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 170: UINT8 IssConfigTdpCoreCount[CONFIG_TDP_MAX_LEVEL]; // get B2P CONFIG_TDP_GET_CORE_COUNT
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 171: UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 172: UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/hob_memmap.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 82: BOOLEAN newDimm; // 0 - DIMM is not new to the system for this boot 1 - DIMM is new to the system for this boot (AEP DIMM only)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 108: UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 154: BOOLEAN IsMapped; // Is this node mapped to system address space
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 160: UINT16 type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 161: UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 164: UINT8 channelInterBitmap[MAX_IMC]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 165: UINT8 FMchannelInterBitmap[MAX_IMC]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 166: UINT8 imcInterBitmap; //Bit map to denote which IMCs are interleaved from this socket.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 169: UINT8 mirrored; //To Indicate the SAD is mirrored while enabling partial mirroring
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 179: UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 194: UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 214: UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 222: UINT8 RasModesSupported; //RAS modes that are supported by current memory population.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 223: UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/msr.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 27: printk(BIOS_DEBUG, "msr %s (0x%x) 0x%x%08x\n", #id, id, msr.hi, msr.lo); \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/in... PS4, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 26: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 31: fmt, ((u32)dev >> 20) & 0xfff, ((u32)dev >> 15) & 0x1f, ((u32)dev >> 12) & 0x07, \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 231: #define PCH_IOAPIC_BUS_NUMBER 0xF0 // TODO - UEFI ACPI table may be wrong
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 237: #define PCH_IOAPIC_ADDRESS IOXAPIC_BASE_ADDRESS // This must get range from Legacy IIO
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/in... PS3, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/in... PS2, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... File src/soc/intel/skylake_sp/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 26: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/in... PS1, Line 31: printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 444: /* find bus, device, and function number for socket ID UBOX device */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 &&
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 452: bus_no, device_no, function_no, vendor_id, device_id);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 468: * Every 3b of the Node ID mapping register maps to a specific node
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 469: * Read the Node ID Mapping Register and find the node that matches
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 470: * the gid read from the Node ID configuration register (above).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
please, no space before tabs
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 499: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 512: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 514: else
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 550: PCU_DEV, PCU_CR1_FUN),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 551: PCU_CR1_BIOS_RESET_CPL_REG);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/so... PS1, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f};
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 444: /* find bus, device, and function number for socket ID UBOX device */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 &&
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 452: bus_no, device_no, function_no, vendor_id, device_id);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 468: * Every 3b of the Node ID mapping register maps to a specific node
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 469: * Read the Node ID Mapping Register and find the node that matches
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 470: * the gid read from the Node ID configuration register (above).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
please, no space before tabs
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 499: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 512: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 514: else
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 550: PCU_DEV, PCU_CR1_FUN),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 551: PCU_CR1_BIOS_RESET_CPL_REG);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/so... PS2, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f};
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 444: /* find bus, device, and function number for socket ID UBOX device */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 &&
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 452: bus_no, device_no, function_no, vendor_id, device_id);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 468: * Every 3b of the Node ID mapping register maps to a specific node
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 469: * Read the Node ID Mapping Register and find the node that matches
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 470: * the gid read from the Node ID configuration register (above).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
please, no space before tabs
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 499: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 512: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 514: else
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 550: PCU_DEV, PCU_CR1_FUN),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 551: PCU_CR1_BIOS_RESET_CPL_REG);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/so... PS3, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f};
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... File src/soc/intel/skylake_sp/soc_util.c:
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 439: printk(BIOS_DEBUG, "Target is remote socket with NodeID 0x%x\n", (target & 0x7));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 444: /* find bus, device, and function number for socket ID UBOX device */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 445: u16 vendor_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 447: u16 device_id = pci_mmio_read_config16(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 449: if (vendor_id != 0xffff && device_id != 0xffff && vendor_id != 0 &&
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 452: bus_no, device_no, function_no, vendor_id, device_id);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 454: u32 bar = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 464: r = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 468: * Every 3b of the Node ID mapping register maps to a specific node
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 469: * Read the Node ID Mapping Register and find the node that matches
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 470: * the gid read from the Node ID configuration register (above).
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 471: * e.g. Bits 2:0 map to node 0, bits 5:3 maps to package 1, etc.
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 473: u32 mapping = pci_mmio_read_config32(PCI_DEV(bus_no, device_no, function_no),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 477: if (nodeid == ((mapping >> (3 * i)) & 0x7)) {
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 486: * nodeid from (B: <above bus>, D:8, F:0, 0:0xc0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 487: * cpubusnos from (B: <above bus>, D:8, F:2, O:0xcc, 0xd0)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
please, no space before tabs
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 489: * (B:<CPUBUSNO1 above>, D:29, F:1, 0:0xc8, 0xcc)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 492: b1 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xcc);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 493: b2 = pci_mmio_read_config32(PCI_DEV(bus_no, 8, 2), 0xd0);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 499: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 502: u32 start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 504: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 512: if (i == 0)
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 513: start_busno = ((b1 >> (stack_id * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 514: else
Too many leading tabs - consider code refactoring
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 515: start_busno = ((b2 >> ((i-1) * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 517: stack_id, start_busno, (r >> (i * 8)) & 0xff);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 550: PCU_DEV, PCU_CR1_FUN),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 551: PCU_CR1_BIOS_RESET_CPL_REG);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 555: (reg >> 9) & 0x1, (reg >> 10) & 0x1, (reg >> 11) & 0x1, (reg >> 12) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 557: (reg >> 1) & 0x1, (reg >> 2) & 0x1, (reg >> 3) & 0x1, (reg >> 4) & 0x1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 623: (u32) (command | PCU_CR1_BIOS_MB_INTERFACE_REG_RUN_BUSY_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 645: (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> MAX_NON_TURBO_LIM_RATIO_SHIFT;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 692: status = write_bios_mailbox_cmd(dev, PCU_CR1_BIOS_MB_CMD_WRITE_PCU_MISC_CONFIG, data);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 707: set_bios_reset_cpl_for_package(socket, 4, 12, 1); /* update RST_CPL3, PCODE_INIT_DONE3 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 709: set_bios_reset_cpl_for_package(socket, 5, 13, 1); /* update RST_CPL4, PCODE_INIT_DONE4 */
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 864: printk(BIOS_DEBUG, "\t\tpirq_reg: x%x, addr: 0x%p, val: 0x%x\n", reg, addr, val);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 911: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 927: if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack?
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1016: IA32_MISC_ENABLE, msr.hi, msr.lo, msr.lo, msr.hi, (msr.lo >> 18) & 0x1,
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1017: (msr.lo & FAST_STRINGS_ENABLE_BIT), (msr.lo & SPEED_STEP_ENABLE_BIT));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1056: MSR_PMG_IO_CAPTURE_BASE, msr.hi, msr.lo, msr.lo & 0xffff, (msr.lo >> 16) & 0x7);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1209: (uint64_t) ((uint64_t)mem_element->BaseAddress << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1211: (uint64_t) ((uint64_t)mem_element->ElementSize << MEM_ADDR_64MB_SHIFT_BITS);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/4/src/soc/intel/skylake_sp/so... PS4, Line 1254: int fixed_msrs[] = {0x250, 0x258, 0x259, 0x268, 0x269, 0x26a, 0x26b, 0x26c, 0x26d, 0x26e, 0x26f};
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/1/src/soc/intel/skylake_sp/un... PS1, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/2/src/soc/intel/skylake_sp/un... PS2, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... File src/soc/intel/skylake_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 151: * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000)
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 191: printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(),
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 192: range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 227: base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10;
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 257: resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1);
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 260: LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 268: LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Ack
https://review.coreboot.org/c/coreboot/+/38548/3/src/soc/intel/skylake_sp/un... PS3, Line 303: LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10));
line over 96 characters
Ack
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 52: Code-Review+2
I think we've beat this patch enough, let's give it the 24-hour treatment and get people unblocked.
Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, Johnny Lin, David Hendricks, Angel Pons, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38548
to look at the new patch set (#53).
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 36 files changed, 5,497 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/53
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
soc/intel: Add Intel Xeon Scalable Processor support
This patch adds support for Intel Xeon-SP.
This patch is developed and verified with Skylake Scalable Processor, which is a processor in Xeon-SP family. The code is expected to be reusable for future geneations of Xeon-SP processors, and will be updated with smaller targeted patches accordingly, to add support for additional Xeon-SP processors, to add features, and to improve the code base.
The Skylake-SP FSP is based on FSP 2.0. The FSP is a proof-of-concept build. The binary is not shared in public, when this patch is upstreamed.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Tested-by: johnny_lin@wiwynn.com Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: David Hendricks david.hendricks@gmail.com --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/xeon_sp/Kconfig A src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/globalnvs.asl A src/soc/intel/xeon_sp/acpi/iiostack.asl A src/soc/intel/xeon_sp/acpi/pci_irq.asl A src/soc/intel/xeon_sp/acpi/uncore.asl A src/soc/intel/xeon_sp/acpi/uncore_irq.asl A src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/chip.c A src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/cpu.c A src/soc/intel/xeon_sp/hob_display.c A src/soc/intel/xeon_sp/include/soc/acpi.h A src/soc/intel/xeon_sp/include/soc/cpu.h A src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h A src/soc/intel/xeon_sp/include/soc/iomap.h A src/soc/intel/xeon_sp/include/soc/irq.h A src/soc/intel/xeon_sp/include/soc/msr.h A src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcr_ids.h A src/soc/intel/xeon_sp/include/soc/pm.h A src/soc/intel/xeon_sp/include/soc/pmc.h A src/soc/intel/xeon_sp/include/soc/ramstage.h A src/soc/intel/xeon_sp/include/soc/romstage.h A src/soc/intel/xeon_sp/include/soc/soc_util.h A src/soc/intel/xeon_sp/lpc.c A src/soc/intel/xeon_sp/reset.c A src/soc/intel/xeon_sp/romstage.c A src/soc/intel/xeon_sp/soc_util.c A src/soc/intel/xeon_sp/spi.c A src/soc/intel/xeon_sp/uncore.c A src/soc/intel/xeon_sp/upd_display.c 36 files changed, 5,497 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 2624644..024a478 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -56,7 +56,7 @@ depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \ - SOC_INTEL_DENVERTON_NS + SOC_INTEL_DENVERTON_NS || SOC_INTEL_XEON_SP help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index e8935b9..47efc4d 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -9,6 +9,7 @@ source "src/soc/intel/skylake/Kconfig" source "src/soc/intel/icelake/Kconfig" source "src/soc/intel/tigerlake/Kconfig" +source "src/soc/intel/xeon_sp/Kconfig"
# Load common config source "src/soc/intel/common/Kconfig" diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig new file mode 100644 index 0000000..8c355c4 --- /dev/null +++ b/src/soc/intel/xeon_sp/Kconfig @@ -0,0 +1,134 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOC_INTEL_XEON_SP + bool + help + Intel Xeon SP support + +if SOC_INTEL_XEON_SP + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + select POSTCAR_CONSOLE + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_RESET + select PLATFORM_USES_FSP2_0 + select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS + select FSP_T_XIP + select FSP_M_XIP + select FSP_USE_REPO + select POSTCAR_STAGE + select IOAPIC + select PARALLEL_MP + select SMP + select INTEL_DESCRIPTOR_MODE_CAPABLE + select COMMON_FADT + select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_TIMER + select SOC_INTEL_COMMON_BLOCK_LPC + select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_SPI + select SOC_INTEL_COMMON_BLOCK_FAST_SPI + select SOC_INTEL_COMMON_BLOCK_PCR + select TSC_MONOTONIC_TIMER + select UDELAY_TSC + select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + +config MAINBOARD_USES_FSP2_0 + bool + default y + +config USE_FSP2_0_DRIVER + def_bool y + depends on MAINBOARD_USES_FSP2_0 + select PLATFORM_USES_FSP2_0 + select UDK_2015_BINDING + select POSTCAR_CONSOLE + select POSTCAR_STAGE + +# Fake FSP binary is used, as the current FSP binary for SKX-SP +# is an engineering build. It is not available to the public +# for now. +config FSP_FD_PATH + string "Location of FSP binary" + depends on FSP_USE_REPO + default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" + +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" + +config MAX_SOCKET + int + default 2 + +# For 2S config, the number of cpus could be as high as +# 2 threads * 20 cores * 2 sockets +config MAX_CPUS + int + default 80 + +config PCR_BASE_ADDRESS + hex + default 0xfd000000 + help + This option allows you to select MMIO Base Address of sideband bus. + +config DCACHE_RAM_BASE + hex + default 0xfe800000 + +config DCACHE_RAM_SIZE + hex + default 0x200000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x10000 + +config MMCONF_BASE_ADDRESS + hex + default 0x80000000 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfff0fdc0 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x7C00 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0xC000 + +config HEAP_SIZE + hex + default 0x80000 + + +endif ## SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc new file mode 100644 index 0000000..9ad3e77 --- /dev/null +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 - 2020 Intel Corporation +## Copyright (C) 2019 - 2020 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_INTEL_XEON_SP),y) + +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm + +bootblock-y += bootblock/bootblock.c +bootblock-y += spi.c + +postcar-y += soc_util.c +postcar-y += spi.c + +romstage-y += soc_util.c +romstage-y += reset.c +romstage-y += romstage.c +romstage-y += soc_util.c +romstage-y += spi.c +romstage-y += hob_display.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c + +ramstage-y += soc_util.c +ramstage-y += uncore.c +ramstage-y += reset.c +ramstage-y += chip.c +ramstage-y += soc_util.c +ramstage-y += lpc.c +ramstage-y += cpu.c +ramstage-y += spi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c +ramstage-y += hob_display.c + +CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include +CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH) + +endif ## CONFIG_SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c new file mode 100644 index 0000000..37dd420 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi.c @@ -0,0 +1,1017 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <intelblocks/acpi.h> +#include <device/pci.h> +#include <cbmem.h> +#include <soc/acpi.h> +#include <soc/cpu.h> +#include <soc/pci_devs.h> +#include <soc/soc_util.h> +#include <soc/pm.h> +#include "chip.h" + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + int32_t scis; + + scis = soc_read_sci_irq_select(); + scis &= SCI_IRQ_SEL; + scis >>= SCI_IRQ_ADJUST; + + /* Determine how SCI is routed. */ + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; +} + +void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); + + /* Update the mem console pointer. */ + if (CONFIG(CONSOLE_CBMEM)) + gnvs->cbmc = (uint32_t)cbmem_find(CBMEM_ID_CONSOLE); +} + +uint32_t soc_read_sci_irq_select(void) +{ + struct device *dev = PCH_DEV_PMC; + + if (!dev) + return 0; + + return pci_read_config32(dev, PMC_ACPI_CNT); +} + +acpi_cstate_t *soc_get_cstate_map(size_t *entries) +{ + *entries = 0; + return NULL; +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); + return current; +} + +unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci = acpi_sci_irq(); + uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + flags |= soc_madt_sci_irq_polarity(sci); + + /* SCI */ + current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + + current += + acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) current, 0xff, 0x0d, 1); + + return current; +} + +static unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) +{ + struct device *cpu; + int num_cpus = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, + num_cpus, cpu->path.apic.apic_id); + } + + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + size_t hob_size = 0; + const uint8_t fsp_hob_iio_universal_data_guid[16] = + FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; + int cur_stack; + + int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; + int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; + + /* Local APICs */ + current = xeonsp_acpi_create_madt_lapics(current); + + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + cur_stack = 0; + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { + const STACK_RES *ri = + &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + // TODO: do we have situation with only bus 0 and one stack? + if (ri->BusBase != ri->BusLimit) { + assert(cur_stack < ARRAY_SIZE(ioapic_ids)); + assert(cur_stack < ARRAY_SIZE(gsi_bases)); + int ioapic_id = ioapic_ids[cur_stack]; + int gsi_base = gsi_bases[cur_stack]; + printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " + "ioapic_base: 0x%x, gsi_base: 0x%x\n", + socket, stack, ioapic_id, ri->IoApicBase, gsi_base); + current += acpi_create_madt_ioapic( + (acpi_madt_ioapic_t *)current, + ioapic_id, ri->IoApicBase, gsi_base); + ++cur_stack; + + if (socket == 0 && stack == 0) { + assert(cur_stack < ARRAY_SIZE(ioapic_ids)); + assert(cur_stack < ARRAY_SIZE(gsi_bases)); + ioapic_id = ioapic_ids[cur_stack]; + gsi_base = gsi_bases[cur_stack]; + printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " + "ioapic_base: 0x%x, gsi_base: 0x%x\n", + socket, stack, ioapic_id, + ri->IoApicBase + 0x1000, gsi_base); + current += acpi_create_madt_ioapic( + (acpi_madt_ioapic_t *)current, + ioapic_id, ri->IoApicBase + 0x1000, gsi_base); + ++cur_stack; + } + } + } + } + + return acpi_madt_irq_overrides(current); +} + +__attribute__ ((weak)) void motherboard_fill_fadt(acpi_fadt_t *fadt) +{ +} + +void generate_t_state_entries(int core, int cores_per_package) +{ +} + +void generate_p_state_entries(int core, int cores_per_package) +{ +} + +void generate_cpu_entries(struct device *device) +{ + int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; + int plen = 6; + int total_threads = dev_count_cpu(); + int threads_per_package = get_threads_per_package(); + int numcpus = total_threads / threads_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each, totalcores: %d.\n", + numcpus, threads_per_package, total_threads); + + for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { + for (core_id = 0; core_id < threads_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor _PR.CPUx */ + acpigen_write_processor((cpu_id) * threads_per_package + + core_id, pcontrol_blk, plen); + + /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ + + /* TODO: Soc specific power states generation */ + acpigen_pop_len(); + } + } + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, threads_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(threads_per_package); +} + +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + uint16_t pmbase = ACPI_BASE_ADDRESS; + + /* System Management */ + if (!CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = 0x00; + fadt->acpi_enable = 0x00; + fadt->acpi_disable = 0x00; + } + + /* Power Control */ + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe1_blk = 0; + + /* Control Registers - Length */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->duty_offset = 1; + fadt->duty_width = 0; + + /* RTC Registers */ + fadt->day_alrm = 0x0D; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + /* Reset Register */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xCF9; + fadt->reset_reg.addrh = 0x00; + fadt->reset_value = 6; + + /* PM1 Status & PM1 Enable */ + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x00; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x00; + + /* PM1 Control Registers */ + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x00; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x00; + + /* PM2 Control Registers */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x00; + + /* PM1 Timer Register */ + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x00; + + /* General-Purpose Event Registers */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x00; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x00; + + motherboard_fill_fadt(fadt); +} + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + /* Use ACPI 3.0 revision */ + fadt->header.revision = get_acpi_table_revision(FADT); + + fadt->sci_int = acpi_sci_irq(); + /* + TODO: enabled SMM mode switch when SMM handlers are set up. + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + */ + fadt->smi_cmd = 0x00; + fadt->acpi_enable = 0x00; + fadt->acpi_disable = 0x00; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; + if (!CONFIG(NO_FADT_8042)) + fadt->iapc_boot_arch |= ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + soc_fill_fadt(fadt); +} + +static acpi_tstate_t xeon_sp_tss_table[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, +}; + +acpi_tstate_t *soc_get_tss_table(int *entries) +{ + *entries = ARRAY_SIZE(xeon_sp_tss_table); + return xeon_sp_tss_table; +} + +int soc_madt_sci_irq_polarity(int sci) +{ + if (sci >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +unsigned long southbridge_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + current = acpi_write_hpet(device, current, rsdp); + current = (ALIGN(current, 16)); + printk(BIOS_DEBUG, "current = %lx\n", current); + return current; +} + +unsigned long acpi_create_srat_lapics(unsigned long current) +{ + struct device *cpu; + int cpu_index = 0; + + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!cpu->enabled) + continue; + printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", + cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, + cpu->path.apic.node_id, cpu->path.apic.apic_id); + cpu_index++; + } + return current; +} + +static unsigned long acpi_fill_srat(unsigned long current) +{ + acpi_srat_mem_t srat_mem[MAX_ACPI_MEMORY_AFFINITY_COUNT]; + unsigned int mem_count; + + /* create all subtables for processors */ + current = acpi_create_srat_lapics(current); + + mem_count = get_srat_memory_entries(srat_mem); + for (int i = 0; i < mem_count; ++i) { + printk(BIOS_DEBUG, "adding srat memory %d entry length: %d, addr: 0x%x%x, " + "length: 0x%x%x, proximity_domain: %d, flags: %x\n", + i, srat_mem[i].length, + srat_mem[i].base_address_high, srat_mem[i].base_address_low, + srat_mem[i].length_high, srat_mem[i].length_low, + srat_mem[i].proximity_domain, srat_mem[i].flags); + memcpy((acpi_srat_mem_t *)current, &srat_mem[i], sizeof(srat_mem[i])); + current += srat_mem[i].length; + } + + return current; +} + +static unsigned long acpi_fill_slit(unsigned long current) +{ + int nodes = get_cpu_count(); + + uint8_t *p = (uint8_t *)current; + memset(p, 0, 8 + nodes * nodes); + *p = (uint8_t)nodes; + p += 8; + + /* this assumes fully connected socket topology */ + for (int i = 0; i < nodes; i++) { + for (int j = 0; j < nodes; j++) { + if (i == j) + p[i*nodes+j] = 10; + else + p[i*nodes+j] = 16; + } + } + + current += 8+nodes*nodes; + return current; +} + +static int get_stack_for_port(int p) +{ + if (p == 0) + return CSTACK; + else if (p >= PORT_1A && p <= PORT_1D) + return PSTACK0; + else if (p >= PORT_2A && p <= PORT_2D) + return PSTACK1; + else if (p >= PORT_3A && p <= PORT_3D) + return PSTACK2; + else if (p >= PORT_4A && p <= PORT_4D) + return PSTACK3; // MCP0 + else + return PSTACK4; // MCP1 +} + +static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) +{ + int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + uint32_t enum_id; + unsigned long tmp = current; + + size_t hob_size; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + uint32_t reg_base = + hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", + __func__, socket, stack, bus, pcie_seg, reg_base); + + // Add DRHD Hardware Unit + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + } else { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + } + + // Add PCH IOAPIC + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, + PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, + PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + } + + // Add IOAPIC entry + enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, + APIC_DEV_NUM, APIC_FUNC_NUM); + + // Add CBDMA devices for CSTACK + if (socket != 0 && stack == CSTACK) { + for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, CBDMA_DEV_NUM, cbdma_func_id); + current += acpi_create_dmar_ds_pci(current, + bus, CBDMA_DEV_NUM, cbdma_func_id); + } + } + + // Add PCIe Ports + if (socket != 0 || stack != CSTACK) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, + bus, dev, func); + } + + // Add VMD + if (hob->PlatformData.VMDStackEnable[socket][stack] && + stack >= PSTACK0 && stack <= PSTACK2) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, + bus, VMD_DEV_NUM, VMD_FUNC_NUM); + } + } + + // Add HPET + if (socket == 0 && stack == CSTACK) { + uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); + uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count + printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", + __func__, hpet_capid, num_hpets); + //BIT 15 + if (num_hpets && (num_hpets != 0x1f) && + (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { + printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); + current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, + HPET_DEV_NUM, HPET0_FUNC_NUM); + } + } + + acpi_dmar_drhd_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_atsr(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + unsigned long tmp = current; + bool first = true; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t bus = hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + "vtd_mmio_cap: 0x%llx\n", + __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); + + // ATSR is applicable only for platform supporting device IOTLBs + // through the VT-d extended capability register + assert(vtd_mmio_cap != 0xffffffffffffffff); + if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 + continue; + + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (socket == 0 && p == 0) + continue; + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + if (first) { + printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " + "PCI Segment Number: 0x%x\n", + 0, pcie_seg); + current += acpi_create_dmar_atsr(current, 0, pcie_seg); + first = 0; + } + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); + } + } + if (tmp != current) + acpi_dmar_atsr_fixup(tmp, current); + } + + return current; +} + +static unsigned long acpi_create_rmrr(unsigned long current) +{ + uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); + + uint32_t *ptr; + + // reserve memory + ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); + if (!ptr) { + ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); + assert(ptr != NULL); + memset(ptr, 0, size); + } + + unsigned long tmp = current; + printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " + "End Address (limit): 0x%x\n", + 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); + current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, + (uint32_t) ((uint32_t) ptr + size - 1)); + + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, + PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_rhsa(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + + printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " + "Proximity Domain: 0x%x\n", vtd_base, socket); + current += acpi_create_dmar_rhsa(current, vtd_base, socket); + } + } + + return current; +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + // DRHD + for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { + int socket = iio; + if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry + socket = 0; + + if (socket == 0) { + for (int stack = 1; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + current = acpi_create_drhd(current, socket, CSTACK); + } else { + for (int stack = 0; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + } + } + + // RMRR + current = acpi_create_rmrr(current); + + // ATSR - causes hang + current = acpi_create_atsr(current); + + // RHSA + current = acpi_create_rhsa(current); + + return current; +} + +unsigned long northbridge_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_dmar_t *dmar; + + const struct soc_intel_xeon_sp_config *const config = config_of(device); + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat, acpi_fill_srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit, acpi_fill_slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + + /* DMAR */ + if (config->vtd_support) { + current = ALIGN(current, 8); + dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", + (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); + acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + } + + return current; +} + +void uncore_inject_dsdt(void) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + acpigen_write_scope("\_SB"); + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + const STACK_RES *ri = &iio_resource.StackRes[stack]; + char rtname[16]; + snprintf(rtname, sizeof(rtname), "RT%02x", + (socket*MAX_IIO_STACK)+stack); + + acpigen_write_name(rtname); + printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", + rtname, socket, stack); + + acpigen_write_resourcetemplate_header(); + + /* bus resource */ + acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, + 0x0, (ri->BusLimit - ri->BusBase + 1)); + + // additional io resources on socket 0 bus 0 + if (socket == 0 && stack == 0) { + /* ACPI 6.4.2.5 I/O Port Descriptor */ + acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); + + /* IO decode CF8-CFF */ + acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, + 0, 0x03B0); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, + 0, 0x0918); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, + 0, 0x000C); + acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, + 0, 0x0020); + } + + /* IO resource */ + acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, + ri->PciResourceIoLimit, 0x0, + (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); + + // additional mem32 resources on socket 0 bus 0 + if (socket == 0 && stack == 0) { + acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, + (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, + VGA_BASE_SIZE); + acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, + (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, + SPI_BASE_SIZE); + } + + /* Mem32 resource */ + acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, + ri->PciResourceMem32Limit, 0x0, + (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); + + /* Mem64 resource */ + acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, + ri->PciResourceMem64Limit, 0x0, + (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); + + acpigen_write_resourcetemplate_footer(); + } + } + acpigen_pop_len(); +} + +void southbridge_inject_dsdt(struct device *device) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); + if (gnvs) + memset(gnvs, 0, sizeof(*gnvs)); + } + + if (gnvs) { + acpi_create_gnvs(gnvs); + /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ + // smm_setup_structures(gnvs, NULL, NULL); + + /* Add it to DSDT. */ + printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); + acpigen_write_scope("\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } + + // Add IIOStack ACPI Resource Templates + uncore_inject_dsdt(); +} diff --git a/src/soc/intel/xeon_sp/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/acpi/globalnvs.asl new file mode 100644 index 0000000..c2d5853 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/globalnvs.asl @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/* Global Variables */ + +Name(\PICM, 0) // IOAPIC/8259 + +/* + * Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we have to fix it up in coreboot's ACPI creation phase. + */ + + +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + OSYS, 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + PRM0, 8, // 0x03 - SMI function parameter + PRM1, 8, // 0x04 - SMI function parameter + SCIF, 8, // 0x05 - SCI function + PRM2, 8, // 0x06 - SCI function parameter + PRM3, 8, // 0x07 - SCI function parameter + LCKF, 8, // 0x08 - Global Lock function for EC + PRM4, 8, // 0x09 - Lock function parameter + PRM5, 8, // 0x0a - Lock function parameter + P80D, 32, // 0x0b - Debug port (IO 0x80) value + LIDS, 8, // 0x0f - LID state (open = 1) + PWRS, 8, // 0x10 - Power State (AC = 1) + PCNT, 8, // 0x11 - Processor count + TPMP, 8, // 0x12 - TPM Present and Enabled + TLVL, 8, // 0x13 - Throttle Level + PPCM, 8, // 0x14 - Maximum P-state usable by OS + PM1I, 64, // 0x15 - PM1 wake status bit + GPEI, 64, // 0x1D - GPE wake status bit + U2WE, 16, // 0x25 - USB2 Wake Enable Bitmap + U3WE, 8, // 0x27 - USB3 Wake Enable Bitmap + + + /* Device Config */ + Offset (0x30), + S5U0, 8, // 0x30 - Enable USB0 in S5 + S5U1, 8, // 0x31 - Enable USB1 in S5 + S3U0, 8, // 0x32 - Enable USB0 in S3 + S3U1, 8, // 0x33 - Enable USB1 in S3 + TACT, 8, // 0x34 - Thermal Active trip point + TPSV, 8, // 0x35 - Thermal Passive trip point + TCRT, 8, // 0x36 - Thermal Critical trip point + DPTE, 8, // 0x37 - Enable DPTF + + /* Base addresses */ + Offset (0x50), + CMEM, 32, // 0x50 - CBMEM TOC + TOLM, 32, // 0x54 - Top of Low Memory + CBMC, 32, // 0x58 - coreboot mem console pointer + MMOB, 32, // 0x5C - MMIO Base Low Base + MMOL, 32, // 0x60 - MMIO Base Low Limit + MMHB, 64, // 0x64 - MMIO Base High Base + MMHL, 64, // 0x6C - MMIO Base High Limit + TSGB, 32, // 0x74 - TSEG Base + TSSZ, 32, // 0x78 - TSEG Size +} diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl new file mode 100644 index 0000000..2d1187f --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define MAKE_IIO_DEV(id,rt) \ + Device (PC##id) \ + { \ + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) \ + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) \ + Name (_UID, 0x##id) \ + Method (_PRT, 0, NotSerialized) \ + { \ + If (PICM) \ + { \ + Return (_SB_.AR##rt) \ + } \ + Return (_SB_.PR##rt) \ + } \ + External(_SB.RT##id) \ + Method (_CRS, 0, NotSerialized) \ + { \ + Return (_SB.RT##id) \ + } \ + Name (SUPP, 0x00) \ + Name (CTRL, 0x00) \ + Name (_PXM, 0x00) /* _PXM: Device Proximity */ \ + Method (_OSC, 4, NotSerialized) \ + { \ + CreateDWordField (Arg3, 0x00, CDW1) \ + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ + { \ + CreateDWordField (Arg3, 0x04, CDW2) \ + If ((Arg2 > 0x02)) \ + { \ + CreateDWordField (Arg3, 0x08, CDW3) \ + } \ + SUPP = CDW2 \ + CTRL = CDW3 \ + If ((AHPE || ((SUPP & 0x16) != 0x16))) \ + { \ + CTRL &= 0x1E \ + Sleep (0x03E8) \ + } \ + /* Never allow SHPC (no SHPC controller in system) */ \ + CTRL &= 0x1D \ + /* Disable Native PCIe AER handling from OS */ \ + CTRL &= 0x17 \ + If ((Arg1 != One)) /* unknown revision */ \ + { \ + CDW1 |= 0x08 \ + } \ + If ((CDW3 != CTRL)) /* capabilities bits were masked */ \ + { \ + CDW1 |= 0x10 \ + } \ + CDW3 = CTRL \ + Return (Arg3) \ + } \ + Else \ + { \ + /* indicate unrecognized UUID */ \ + CDW1 |= 0x04 \ + IO80 = 0xEE \ + Return (Arg3) \ + } \ + } \ + } + +MAKE_IIO_DEV(00, 00) +MAKE_IIO_DEV(01, 10) +MAKE_IIO_DEV(02, 20) +MAKE_IIO_DEV(03, 28) + +#if MAX_SOCKET > 1 +MAKE_IIO_DEV(06, 40) +MAKE_IIO_DEV(07, 50) +MAKE_IIO_DEV(08, 60) +MAKE_IIO_DEV(09, 68) +#endif diff --git a/src/soc/intel/xeon_sp/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/acpi/pci_irq.asl new file mode 100644 index 0000000..cfa4ad5 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/pci_irq.asl @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11 + * CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100 + * (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100 + * + * PIRQ routing control is in PCR ITSS region. + */ + +OperationRegion (ITSS, SystemMemory, + Add (PCR_ITSS_PIRQA_ROUT, + Add (CONFIG_PCR_BASE_ADDRESS, + ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) +Field (ITSS, ByteAcc, NoLock, Preserve) +{ + PIRA, 8, /* PIRQA Routing Control */ + PIRB, 8, /* PIRQB Routing Control */ + PIRC, 8, /* PIRQC Routing Control */ + PIRD, 8, /* PIRQD Routing Control */ + PIRE, 8, /* PIRQE Routing Control */ + PIRF, 8, /* PIRQF Routing Control */ + PIRG, 8, /* PIRQG Routing Control */ + PIRH, 8, /* PIRQH Routing Control */ +} + +Name (IREN, 0x80) /* Interrupt Routing Enable */ +Name (IREM, 0x0f) /* Interrupt Routing Mask */ + +Name (PRSA, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared, ) + {3,4,5,6,7,10,11,12,14,15} +}) +Alias (PRSA, PRSB) +Name (PRSC, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared, ) + {3,4,5,6,10,11,12,14,15} +}) +Alias (PRSC, PRSD) +Alias (PRSA, PRSE) +Alias (PRSA, PRSF) +Alias (PRSA, PRSG) +Alias (PRSA, PRSH) + +#define MAKE_LINK_DEV(id,uid) \ + Device (LNK##id) \ + { \ + Name (_HID, EISAID ("PNP0C0F")) \ + Name (_UID, ##uid) \ + Method (_PRS, 0, NotSerialized) \ + { \ + Return (PRS##id) \ + } \ + Method (_CRS, 0, Serialized) \ + { \ + Name (RTLA, ResourceTemplate () \ + { \ + IRQ (Level, ActiveLow, Shared) {} \ + }) \ + CreateWordField (RTLA, 1, IRQ0) \ + Store (Zero, IRQ0) \ + \ + /* Set the bit from PIRQ Routing Register */ \ + ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ + Return (RTLA) \ + } \ + Method (_SRS, 1, Serialized) \ + { \ + CreateWordField (Arg0, 1, IRQ0) \ + FindSetRightBit (IRQ0, Local0) \ + Decrement (Local0) \ + Store (Local0, ^^PIR##id) \ + } \ + Method (_STA, 0, Serialized) \ + { \ + If (And (^^PIR##id, ^^IREN)) { \ + Return (0x9) \ + } Else { \ + Return (0xb) \ + } \ + } \ + Method (_DIS, 0, Serialized) \ + { \ + Or (^^PIR##id, ^^IREN, ^^PIR##id) \ + } \ + } + +MAKE_LINK_DEV(A,1) +MAKE_LINK_DEV(B,2) +MAKE_LINK_DEV(C,3) +MAKE_LINK_DEV(D,4) +MAKE_LINK_DEV(E,5) +MAKE_LINK_DEV(F,6) +MAKE_LINK_DEV(G,7) +MAKE_LINK_DEV(H,8) diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/uncore.asl new file mode 100644 index 0000000..35fbf98 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/uncore.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/iomap.h> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Scope() +{ + // Private Chipset Register(PCR). Memory Mapped through ILB + OperationRegion(PCRR, SystemMemory, P2SB_BAR, 0x01000000) + Field(PCRR, DWordAcc, Lock, Preserve) + { + Offset (0xD03100), // Interrupt Routing Registers + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } +} + +Scope (_SB) +{ + #include "pci_irq.asl" + #include "uncore_irq.asl" + #include "iiostack.asl" +} diff --git a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl new file mode 100644 index 0000000..8492725 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl @@ -0,0 +1,566 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Uncore devices PCI interrupt routing packages. + * See ACPI spec 6.2.13 _PRT (PCI routing table) for details. + * The mapping fields ae Address, Pin, Source, Source Index. + */ + +#define GEN_PCIE_LEGACY_IRQ() \ + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ + Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ + Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ + Package (0x04) { 0x0003FFFF, 0x00, LNKA, 0x00 } + +#define GEN_UNCORE_LEGACY_IRQ(dev) \ + Package (0x04) { ##dev, 0x00, LNKA, 0x00 }, \ + Package (0x04) { ##dev, 0x01, LNKB, 0x00 }, \ + Package (0x04) { ##dev, 0x02, LNKC, 0x00 }, \ + Package (0x04) { ##dev, 0x03, LNKD, 0x00 } + +#define GEN_PCIE_IOAPIC_IRQ(irq) \ + Package (0x04) { 0x0000FFFF, 0x00, 0x00, ##irq }, \ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, ##irq }, \ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, ##irq }, \ + Package (0x04) { 0x0003FFFF, 0x00, 0x00, ##irq } + +#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ + Package (0x04) { ##dev, 0x00, 0x00, ##irq1 }, \ + Package (0x04) { ##dev, 0x01, 0x00, ##irq2 }, \ + Package (0x04) { ##dev, 0x02, 0x00, ##irq3 }, \ + Package (0x04) { ##dev, 0x03, 0x00, ##irq4 } + +// Socket 0, IIOStack 0 device legacy interrupt routing +Name (PR00, Package (0x28) +{ + // [DMI0]: Legacy PCI Express Port 0 + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + // [CB0A]: CBDMA + // [CB0E]: CBDMA + Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + // [CB0B]: CBDMA + // [CB0F]: CBDMA + Package (0x04) { 0x0004FFFF, 0x01, LNKB, 0x00 }, + // [CB0C]: CBDMA + // [CB0G]: CBDMA + Package (0x04) { 0x0004FFFF, 0x02, LNKC, 0x00 }, + // [CB0D]: CBDMA + // [CB0H]: CBDMA + Package (0x04) { 0x0004FFFF, 0x03, LNKD, 0x00 }, + // Uncore 0 UBOX Device + Package (0x04) { 0x0008FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x03, LNKD, 0x00 }, + // [DISP]: Display Controller + Package (0x04) { 0x000FFFFF, 0x00, LNKA, 0x00 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 }, + // [IHC2]: HECI #2 + Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package (0x04) { 0x0011FFFF, 0x00, LNKA, 0x00 }, + // // [XHCI]: xHCI controller 1 on PCH + Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, + // [TERM]: Thermal Subsystem on PCH + Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, + // [CAMR]: Camera IO Host Controller on PCH + Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package (0x04) { 0x0016FFFF, 0x00, LNKA, 0x00 }, + // [HEC2]: HECI #2 on PCH + Package (0x04) { 0x0016FFFF, 0x01, LNKB, 0x00 }, + // [IDER]: ME IDE redirect on PCH + Package (0x04) { 0x0016FFFF, 0x02, LNKC, 0x00 }, + // [MEKT]: MEKT on PCH + Package (0x04) { 0x0016FFFF, 0x03, LNKD, 0x00 }, + // [SAT1]: SATA controller 1 on PCH + Package (0x04) { 0x0017FFFF, 0x00, LNKA, 0x00 }, + // [NAN1]: NAND Cycle Router on PCH + Package (0x04) { 0x0018FFFF, 0x00, LNKA, 0x00 }, + // [RP17]: PCIE PCH Root Port #17 + Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + // [RP18]: PCIE PCH Root Port #18 + Package (0x04) { 0x001BFFFF, 0x01, LNKB, 0x00 }, + // [RP19]: PCIE PCH Root Port #19 + Package (0x04) { 0x001BFFFF, 0x02, LNKC, 0x00 }, + // [RP20]: PCIE PCH Root Port #20 + Package (0x04) { 0x001BFFFF, 0x03, LNKD, 0x00 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package (0x04) { 0x001DFFFF, 0x00, LNKA, 0x00 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package (0x04) { 0x001DFFFF, 0x01, LNKB, 0x00 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package (0x04) { 0x001DFFFF, 0x03, LNKD, 0x00 }, + // [UAR0]: UART #0 on PCH + Package (0x04) { 0x001EFFFF, 0x02, LNKC, 0x00 }, + // [UAR1]: UART #1 on PCH + Package (0x04) { 0x001EFFFF, 0x03, LNKD, 0x00 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package (0x04) { 0x001FFFFF, 0x00, LNKA, 0x00 }, +}) + +// Socket 0, IIOStack 0 device IOAPIC interrupt routing +Name (AR00, Package (0x28) +{ + // [DMI0]: Legacy PCI Express Port 0 + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1F }, + // [CB0A]: CB3DMA + // [CB0E]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, + // [CB0B]: CB3DMA + // [CB0F]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + // [CB0C]: CB3DMA + // [CB0G]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + // [CB0D]: CB3DMA + // [CB0H]: CB3DMA + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + // [UBX0]: Uncore 0 UBOX Device + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, + Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x1C }, + Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1D }, + Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1E }, + // [DISP]: Display Controller + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x10 }, + // [IHC1]: HECI #1 + // [IHC3]: HECI #3 + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x10 }, + // [IHC2]: HECI #2 + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x11 }, + // [IIDR]: IDE-Redirection (IDE-R) + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x12 }, + // [IMKT]: Keyboard and Text (KT) Redirection + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x13 }, + // [SAT2]: sSATA Host controller 2 on PCH + Package (0x04) { 0x0011FFFF, 0x00, 0x00, 0x10 }, + // [XHCI]: xHCI controller 1 on PCH + Package (0x04) { 0x0014FFFF, 0x00, 0x00, 0x10 }, + // [OTG0]: USB Device Controller (OTG) on PCH + Package (0x04) { 0x0014FFFF, 0x01, 0x00, 0x11 }, + // [TERM]: Thermal Subsystem on PCH + Package (0x04) { 0x0014FFFF, 0x02, 0x00, 0x12 }, + // [CAMR]: Camera IO Host Controller on PCH + Package (0x04) { 0x0014FFFF, 0x03, 0x00, 0x13 }, + // [HEC1]: HECI #1 on PCH + // [HEC3]: HECI #3 on PCH + Package (0x04) { 0x0016FFFF, 0x00, 0x00, 0x10 }, + // [HEC2]: HECI #2 on PCH + Package (0x04) { 0x0016FFFF, 0x01, 0x00, 0x11 }, + // [IDER]: ME IDE redirect on PCH + Package (0x04) { 0x0016FFFF, 0x02, 0x00, 0x12 }, + // [MEKT]: MEKT on PCH + Package (0x04) { 0x0016FFFF, 0x03, 0x00, 0x13 }, + // [SAT1]: SATA controller 1 on PCH + Package (0x04) { 0x0017FFFF, 0x00, 0x00, 0x10 }, + // [NAN1]: NAND Cycle Router on PCH + Package (0x04) { 0x0018FFFF, 0x00, 0x00, 0x10 }, + // [RP17]: PCIE PCH Root Port #17 + Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 }, + // [RP18]: PCIE PCH Root Port #18 + Package (0x04) { 0x001BFFFF, 0x01, 0x00, 0x11 }, + // [RP19]: PCIE PCH Root Port #19 + Package (0x04) { 0x001BFFFF, 0x02, 0x00, 0x12 }, + // [RP20]: PCIE PCH Root Port #20 + Package (0x04) { 0x001BFFFF, 0x03, 0x00, 0x13 }, + // [RP01]: PCIE PCH Root Port #1 + // [RP05]: PCIE PCH Root Port #5 + Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, + // [RP02]: PCIE PCH Root Port #2 + // [RP06]: PCIE PCH Root Port #6 + Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, + // [RP03]: PCIE PCH Root Port #3 + // [RP07]: PCIE PCH Root Port #7 + Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, + // [RP04]: PCIE PCH Root Port #4 + // [RP08]: PCIE PCH Root Port #8 + Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, + // [RP09]: PCIE PCH Root Port #9 + // [RP13]: PCIE PCH Root Port #13 + Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 }, + // [RP10]: PCIE PCH Root Port #10 + // [RP14]: PCIE PCH Root Port #14 + Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x11 }, + // [RP11]: PCIE PCH Root Port #11 + // [RP15]: PCIE PCH Root Port #15 + Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 }, + // [RP12]: PCIE PCH Root Port #12 + // [RP16]: PCIE PCH Root Port #16 + Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x13 }, + // [UAR0]: UART #0 on PCH + Package (0x04) { 0x001EFFFF, 0x02, 0x00, 0x16 }, + // [UAR1]: UART #1 on PCH + Package (0x04) { 0x001EFFFF, 0x03, 0x00, 0x17 }, + // [CAVS]: HD Audio Subsystem Controller on PCH + // [SMBS]: SMBus controller on PCH + // [GBE1]: GbE Controller on PCH + // [NTPK]: Northpeak Controller on PCH + Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x10 }, +}) + +// Socket 0, IIOStack 1 device legacy interrupt routing +Name (PR10, Package (0x40) +{ + // PCI Express Port 1A-1D + GEN_PCIE_LEGACY_IRQ(), + + // Uncore CHAUTIL Devices + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + + // Uncore CHASAD Devices + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), + + // Uncore CMSCHA Devices + GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), + + // Uncore CHASADALL Device + GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), + + // Uncore PCUCR Device + GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), + + // Uncore VCUCR Device + GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) +}) + +// Socket 0, IIOStack 1 device IOAPIC interrupt routing +Name (AR10, Package (0x40) +{ + // PCI Express Port 1A-1D + GEN_PCIE_IOAPIC_IRQ(0x27), + + // Uncore CHAUTIL Devices + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore CHASAD Devices + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore CMSCHA Devices + GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x20, 0x24, 0x25, 0x26), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore CHASADALL Device + GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore PCUCR Device + GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x20, 0x24, 0x25, 0x26), + + // Uncore VCUCR Device + GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x20, 0x24, 0x25, 0x26) +}) + +// Socket 0, IIOStack 2 device legacy interrupt routing +Name (PR20, Package (0x24) +{ + // PCI Express Port 2 on PC02 + GEN_PCIE_LEGACY_IRQ(), + + // Uncore M2MEM Devices + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + + // Uncore MCMAIN Device + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + + // Uncore MCDECS2 Device + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + + // Uncore MCMAIN Device + GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), + + // Uncore MCDECS Device + GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), + + // Uncore Unicast MC0 DDRIO0 Device + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + + // Uncore Unicast MC1 DDRIO0 Device + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 0, IIOStack 2 device IOAPIC interrupt routing +Name (AR20, Package (0x24) +{ + // PCI Express Port 2 on PC02 + GEN_PCIE_IOAPIC_IRQ(0x2F), + + // Uncore M2MEM Devices + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x28, 0x2C, 0x2D, 0x2E), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCMAIN Device + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCDECS2 Device + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCMAIN Device + GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore MCDECS Device + GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore Unicast MC0 DDRIO0 Device + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x28, 0x2C, 0x2D, 0x2E), + + // Uncore Unicast MC1 DDRIO0 Device + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x28, 0x2C, 0x2D, 0x2E) +}) + +// Socket 0, IIOStack 3 device legacy interrupt routing +Name (PR28, Package (0x20) +{ + // PCI Express Port 3 on PC03 + GEN_PCIE_LEGACY_IRQ(), + + // KTI Devices + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + + // M3K Device + GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), + + // M2U Device + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + + // M2D Device + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + + // M20 Device + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 0, IIOStack 3 device IOAPIC interrupt routing +Name (AR28, Package (0x20) +{ + // PCI Express Port 3 on PC03 + GEN_PCIE_IOAPIC_IRQ(0x37), + + // KTI Devices + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x30, 0x34, 0x35, 0x36), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x30, 0x34, 0x35, 0x36), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x30, 0x34, 0x35, 0x36), + + // M3K Device + GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x30, 0x34, 0x35, 0x36), + + // M2U Device + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x30, 0x34, 0x35, 0x36), + + // M2D Device + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x30, 0x34, 0x35, 0x36), + + // M20 Device + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x30, 0x34, 0x35, 0x36) +}) + +// Socket 1, IIOStack 0 device legacy interrupt routing +Name (PR40, Package (0x09) +{ + // DMI + Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + + // CBDMA + GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), + + // Ubox + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF) +}) + +// Socket 1, IIOStack 0 device IOAPIC interrupt routing +Name (AR40, Package (0x09) +{ + // DMI + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x4F }, + + // CBDMA + GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B), + + // Ubox + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x48, 0x4C, 0x4D, 0x4E), +}) + +// Socket 1, IIOStack 1 device legacy interrupt routing +Name (PR50, Package (0x40) +{ + // PCI Express Port + GEN_PCIE_LEGACY_IRQ(), + + // CHA Devices + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), + GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), + + // PCU Devices + GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) +}) + +// Socket 1, IIOStack 1 device IOAPIC interrupt routing +Name (AR50, Package (0x40) +{ + // PCI Express Port + GEN_PCIE_IOAPIC_IRQ(0x57), + + // CHA Devices + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x50, 0x54, 0x55, 0x56), + + // PCU Devices + GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x50, 0x54, 0x55, 0x56), + GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x50, 0x54, 0x55, 0x56) +}) + +// Socket 1, IIOStack 2 device legacy interrupt routing +Name (PR60, Package (0x24) +{ + // PCI Express Port + GEN_PCIE_LEGACY_IRQ(), + + // Integrated Memory Controller + GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), + + // Uncore Devices + GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 1, IIOStack 2 device IOAPIC interrupt routing +Name (AR60, Package (0x24) +{ + // PCI Express Port + GEN_PCIE_IOAPIC_IRQ(0x5F), + + // Integrated Memory Controller + GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x58, 0x5C, 0x5D, 0x5E), + + // Uncore Devices + GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x58, 0x5C, 0x5D, 0x5E), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x58, 0x5C, 0x5D, 0x5E) +}) + +// Socket 1, IIOStack 3 device legacy interrupt routing +Name (PR68, Package (0x20) +{ + // PCI Express Port + GEN_PCIE_LEGACY_IRQ(), + + // Uncore Devices + GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), + GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), + GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), + GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) +}) + +// Socket 1, IIOStack 3 device legacy interrupt routing +Name (AR68, Package (0x20) +{ + // PCI Express Port + GEN_PCIE_IOAPIC_IRQ(0x67), + + // Uncore Devices + GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x60, 0x64, 0x65, 0x66), + GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x60, 0x64, 0x65, 0x66) +}) diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c new file mode 100644 index 0000000..482f5b5 --- /dev/null +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pci.h> +#include <FsptUpd.h> +#include <intelblocks/fast_spi.h> +#include <soc/iomap.h> +#include <console/console.h> + +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = FSPT_UPD_SIGNATURE, + .Revision = 1, + .Reserved = {0}, + }, + .FsptCoreUpd = { + .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, + .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, + .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, + .Reserved1 = {0}, + }, + .FsptConfig = { + .PcdFsptPort80RouteDisable = 0, + .ReservedTempRamInitUpd = {0}, + }, + .UnusedUpdSpace0 = {0}, + .UpdTerminator = 0x55AA, +}; + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + fast_spi_cache_bios_region(); + + bootblock_main_with_basetime(base_timestamp); +} + +void bootblock_soc_early_init(void) +{ + fast_spi_early_init(SPI_BASE_ADDRESS); +} + +void bootblock_soc_init(void) +{ + if (CONFIG(BOOTBLOCK_CONSOLE)) + printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); +} diff --git a/src/soc/intel/xeon_sp/chip.c b/src/soc/intel/xeon_sp/chip.c new file mode 100644 index 0000000..832f98e --- /dev/null +++ b/src/soc/intel/xeon_sp/chip.c @@ -0,0 +1,603 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <assert.h> +#include <device/pci.h> +#include <soc/acpi.h> +#include <soc/ramstage.h> +#include <soc/soc_util.h> + +struct pci_resource { + struct device *dev; + struct resource *res; + struct pci_resource *next; +}; + +struct stack_dev_resource { + uint8_t align; + struct pci_resource *children; + struct stack_dev_resource *next; +}; + +static void assign_stack_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge); + +static void xeonsp_pci_domain_scan_bus(struct device *dev) +{ + DEV_FUNC_ENTER(dev); + struct bus *link = dev->link_list; + + printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", + __FILE__, __func__, dev_path(dev)); + while (link != NULL) { + if (link->secondary == 0) { // scan only PSTACK buses + struct device *d; + for (d = link->children; d; d = d->sibling) + pci_probe_dev(d, link, d->path.pci.devfn); + scan_bridges(link); + } else { + pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); + } + link = link->next; + } + DEV_FUNC_EXIT(dev); +} + +static void xeonsp_pci_dev_iterator(struct bus *bus, + void (*dev_iterator)(struct device *, void *), + void (*res_iterator)(struct device *, struct resource *, void *), + void *data) +{ + struct device *curdev; + struct resource *res; + + /* Walk through all devices and find which resources they need. */ + for (curdev = bus->children; curdev; curdev = curdev->sibling) { + struct bus *link; + + if (!curdev->enabled) + continue; + + if (!curdev->ops || !curdev->ops->read_resources) { + if (curdev->path.type != DEVICE_PATH_APIC) + printk(BIOS_ERR, "%s missing read_resources\n", + dev_path(curdev)); + continue; + } + + if (dev_iterator) + dev_iterator(curdev, data); + + if (res_iterator) { + for (res = curdev->resource_list; res; res = res->next) + res_iterator(curdev, res, data); + } + + /* Read in the resources behind the current device's links. */ + for (link = curdev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); + } +} + +static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) +{ + post_log_path(dev); + dev->ops->read_resources(dev); +} + +static void xeonsp_pci_dev_dummy_func(struct device *dev) +{ +} + +static void xeonsp_reset_pci_op(struct device *dev, void *data) +{ + if (dev->ops) + dev->ops->read_resources = xeonsp_pci_dev_dummy_func; +} + +static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) +{ + for (int i = 0; i < info->no_of_stacks; ++i) { + if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) + return &info->res[i]; + } + return NULL; +} + +static void add_res_to_stack(struct stack_dev_resource **root, + struct device *dev, struct resource *res) +{ + struct stack_dev_resource *cur = *root; + while (cur) { + if (cur->align == res->align || cur->next == NULL) /* equal or last record */ + break; + else if (cur->align > res->align) { + if (cur->next->align < res->align) /* need to insert new record here */ + break; + cur = cur->next; + } else { + break; + } + } + + struct stack_dev_resource *nr; + if (!cur || cur->align != res->align) { /* need to add new record */ + nr = malloc(sizeof(struct stack_dev_resource)); + if (nr == 0) + die("assign_resource_to_stack(): out of memory.\n"); + memset(nr, 0, sizeof(struct stack_dev_resource)); + nr->align = res->align; + if (!cur) { + *root = nr; /* head node */ + } else if (cur->align > nr->align) { + if (cur->next == NULL) { + cur->next = nr; + } else { + nr->next = cur->next; + cur->next = nr; + } + } else { /* insert in the beginning */ + nr->next = cur; + *root = nr; + } + } else { + nr = cur; + } + + assert(nr != NULL && nr->align == res->align); + + struct pci_resource *npr = malloc(sizeof(struct pci_resource)); + if (npr == NULL) + die("%s: out of memory.\n", __func__); + npr->res = res; + npr->dev = dev; + npr->next = NULL; + + if (nr->children == NULL) { + nr->children = npr; + } else { + struct pci_resource *pr = nr->children; + while (pr->next != NULL) + pr = pr->next; + pr->next = npr; + } +} + +static void reserve_dev_resources(STACK_RES *stack, unsigned long res_type, + struct stack_dev_resource *res_root, struct resource *bridge) +{ + uint8_t align; + uint64_t orig_base, base; + + if (res_type & IORESOURCE_IO) + orig_base = stack->PciResourceIoBase; + else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || + (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) + orig_base = stack->PciResourceMem64Base; + else + orig_base = stack->PciResourceMem32Base; + + align = 0; + base = orig_base; + int first = 1; + while (res_root) { /* loop through all devices grouped by alignment requirements */ + struct pci_resource *pr = res_root->children; + while (pr) { + if (first) { + if (bridge) { /* takes highest alignment */ + if (bridge->align < pr->res->align) + bridge->align = pr->res->align; + orig_base = ALIGN_UP(orig_base, 1 << bridge->align); + } else { + orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); + } + base = orig_base; + + if (bridge) + bridge->base = base; + pr->res->base = base; + first = 0; + } else { + pr->res->base = ALIGN_UP(base, 1 << pr->res->align); + } + pr->res->limit = pr->res->base + pr->res->size - 1; + base = pr->res->limit + 1; + pr->res->flags |= (IORESOURCE_ASSIGNED); + pr = pr->next; + } + res_root = res_root->next; + } + + if (bridge) { + /* this bridge doesn't have any resources, will set it to default window */ + if (first) { + orig_base = ALIGN_UP(orig_base, 1 << bridge->align); + bridge->base = orig_base; + base = orig_base + (1ULL << bridge->gran); + } + + bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; + + bridge->limit = bridge->base + bridge->size - 1; + bridge->flags |= (IORESOURCE_ASSIGNED); + base = bridge->limit + 1; + } + + /* update new limits */ + if (res_type & IORESOURCE_IO) + stack->PciResourceIoBase = base; + else if ((res_type & IORESOURCE_MEM) && ((res_type & IORESOURCE_PCI64) || + (!res_root && bridge && (bridge->flags & IORESOURCE_PREFETCH)))) + stack->PciResourceMem64Base = base; + else + stack->PciResourceMem32Base = base; +} + +static void reclaim_resource_mem(struct stack_dev_resource *res_root) +{ + while (res_root) { /* loop through all devices grouped by alignment requirements */ + /* free pci_resource */ + struct pci_resource *pr = res_root->children; + while (pr) { + struct pci_resource *dpr = pr; + pr = pr->next; + free(dpr); + } + + /* free stack_dev_resource */ + struct stack_dev_resource *ddr = res_root; + res_root = res_root->next; + free(ddr); + } +} + +static void assign_bridge_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge) +{ + struct resource *res; + if (!dev->enabled) + return; + + for (res = dev->resource_list; res; res = res->next) { + if (!(res->flags & IORESOURCE_BRIDGE) || + (bridge && ((bridge->flags & (IORESOURCE_IO | IORESOURCE_MEM | + IORESOURCE_PREFETCH | IORESOURCE_PCI64)) != + (res->flags & (IORESOURCE_IO | IORESOURCE_MEM | + IORESOURCE_PREFETCH | IORESOURCE_PCI64))))) + continue; + + assign_stack_resources(stack_list, dev, res); + if (!bridge) + continue; + /* for 1st time update, overlading IORESOURCE_ASSIGNED */ + if (!(bridge->flags & IORESOURCE_ASSIGNED)) { + bridge->base = res->base; + bridge->limit = res->limit; + bridge->flags |= (IORESOURCE_ASSIGNED); + } else { + /* update bridge range from child bridge range */ + if (res->base < bridge->base) + bridge->base = res->base; + if (res->limit > bridge->limit) + bridge->limit = res->limit; + } + bridge->size = (bridge->limit - bridge->base + 1); + } +} + +static void assign_stack_resources(struct iiostack_resource *stack_list, + struct device *dev, struct resource *bridge) +{ + struct bus *bus; + + /* Read in the resources behind the current device's links. */ + for (bus = dev->link_list; bus; bus = bus->next) { + struct device *curdev; + STACK_RES *stack; + + /* get IIO stack for this bus */ + stack = find_stack_for_bus(stack_list, bus->secondary); + assert(stack != NULL); + + /* Assign resources to bridge */ + for (curdev = bus->children; curdev; curdev = curdev->sibling) + assign_bridge_resources(stack_list, curdev, bridge); + + /* Pick non-bridged resources for resource allocation for each resource type */ + unsigned long flags[5] = {IORESOURCE_IO, IORESOURCE_MEM, + (IORESOURCE_PCI64|IORESOURCE_MEM), (IORESOURCE_MEM|IORESOURCE_PREFETCH), + (IORESOURCE_PCI64|IORESOURCE_MEM|IORESOURCE_PREFETCH)}; + uint8_t no_res_types = 5; + if (bridge) { + flags[0] = bridge->flags & + (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); + if ((bridge->flags & IORESOURCE_MEM) && + (bridge->flags & IORESOURCE_PREFETCH)) + flags[0] |= IORESOURCE_PCI64; + no_res_types = 1; + } + + /* Process each resource type */ + for (int rt = 0; rt < no_res_types; ++rt) { + struct stack_dev_resource *res_root = NULL; + + for (curdev = bus->children; curdev; curdev = curdev->sibling) { + struct resource *res; + if (!curdev->enabled) + continue; + + for (res = curdev->resource_list; res; res = res->next) { + if ((res->flags & IORESOURCE_BRIDGE) || (res->flags & + (IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_ASSIGNED) + ) || ((res->flags & (IORESOURCE_IO | + IORESOURCE_MEM | IORESOURCE_PCI64 + | IORESOURCE_PREFETCH)) + != flags[rt]) || res->size == 0) + continue; + else + add_res_to_stack(&res_root, curdev, res); + } + } + + /* Allocate resources and update bridge range */ + if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { + reserve_dev_resources(stack, flags[rt], res_root, bridge); + reclaim_resource_mem(res_root); + } + } + } +} + +static void xeonsp_constrain_pci_resources(struct device *dev, struct resource *res, void *data) +{ + STACK_RES *stack = (STACK_RES *) data; + if (!(res->flags & IORESOURCE_FIXED)) + return; + + uint64_t base, limit; + if (res->flags & IORESOURCE_IO) { + base = stack->PciResourceIoBase; + limit = stack->PciResourceIoLimit; + } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { + base = stack->PciResourceMem64Base; + limit = stack->PciResourceMem64Limit; + } else { + base = stack->PciResourceMem32Base; + limit = stack->PciResourceMem32Limit; + } + + if (((res->base + res->size - 1) < base) || (res->base > limit)) /* outside window */ + return; + + if (res->limit > limit) /* resource end is out of limit */ + limit = res->base - 1; + else + base = res->base + res->size; + + if (res->flags & IORESOURCE_IO) { + stack->PciResourceIoBase = base; + stack->PciResourceIoLimit = limit; + } else if ((res->flags & IORESOURCE_MEM) && (res->flags & IORESOURCE_PCI64)) { + stack->PciResourceMem64Base = base; + stack->PciResourceMem64Limit = limit; + } else { + stack->PciResourceMem32Base = base; + stack->PciResourceMem32Limit = limit; + } +} + +static void xeonsp_pci_domain_read_resources(struct device *dev) +{ + struct bus *link; + + DEV_FUNC_ENTER(dev); + + pci_domain_read_resources(dev); + + /* + * Walk through all devices in this domain and read resources. + * Since there is no callback when read resource operation is + * complete for all devices, domain read resource function initiates + * read resources for all devices and swaps read resource operation + * with dummy function to avoid warning. + */ + for (link = dev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); + + for (link = dev->link_list; link; link = link->next) + xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); + + /* + * 1. group devices, resources for each stack + * 2. order resources in descending order of requested resource allocation sizes + */ + struct iiostack_resource stack_info = {0}; + get_iiostack_info(&stack_info); + + /* constrain stack window */ + for (link = dev->link_list; link; link = link->next) { + STACK_RES *stack = find_stack_for_bus(&stack_info, link->secondary); + assert(stack != 0); + xeonsp_pci_dev_iterator(link, NULL, xeonsp_constrain_pci_resources, stack); + } + + /* assign resources */ + assign_stack_resources(&stack_info, dev, NULL); + + DEV_FUNC_EXIT(dev); +} + +static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) +{ + if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && + !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { + res->flags &= ~IORESOURCE_ASSIGNED; + } +} + +static void xeonsp_pci_domain_set_resources(struct device *dev) +{ + DEV_FUNC_ENTER(dev); + + print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); + + /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ + xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); + + /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ + xeonsp_pci_domain_read_resources(dev); + + struct bus *link = dev->link_list; + while (link != NULL) { + assign_resources(link); + link = link->next; + } + + print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); + + DEV_FUNC_EXIT(dev); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &xeonsp_pci_domain_set_resources, + .scan_bus = &xeonsp_pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = &northbridge_write_acpi_tables, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = xeon_sp_init_cpus, + .scan_bus = NULL, +#if CONFIG(HAVE_ACPI_TABLES) + /* defined in src/soc/intel/common/block/acpi/acpi.c */ + .acpi_fill_ssdt_generator = generate_cpu_entries, +#endif +}; + +/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ +static void attach_iio_stacks(struct device *dev) +{ + struct bus *iiostack_bus; + struct device dummy; + struct iiostack_resource stack_info = {0}; + + DEV_FUNC_ENTER(dev); + + get_iiostack_info(&stack_info); + for (int s = 0; s < stack_info.no_of_stacks; ++s) { + /* only non zero bus no. needs to be enumerated */ + if (stack_info.res[s].BusBase == 0) + continue; + + iiostack_bus = malloc(sizeof(struct bus)); + if (iiostack_bus == NULL) + die("%s: out of memory.\n", __func__); + memset(iiostack_bus, 0, sizeof(*iiostack_bus)); + memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); + iiostack_bus->secondary = stack_info.res[s].BusBase; + iiostack_bus->subordinate = stack_info.res[s].BusBase; + iiostack_bus->dev = NULL; + iiostack_bus->children = NULL; + iiostack_bus->next = NULL; + iiostack_bus->link_num = 1; + + dummy.bus = iiostack_bus; + dummy.path.type = DEVICE_PATH_PCI; + dummy.path.pci.devfn = 0; + uint32_t id = pci_read_config32(&dummy, PCI_VENDOR_ID); + if (id == 0xffffffff) + printk(BIOS_WARNING, "IIO Stack device %s not visible\n", + dev_path(&dummy)); + + if (dev->link_list == NULL) { + dev->link_list = iiostack_bus; + } else { + struct bus *nlink = dev->link_list; + while (nlink->next != NULL) + nlink = nlink->next; + nlink->next = iiostack_bus; + } + } + + DEV_FUNC_EXIT(dev); +} + +static void soc_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + attach_iio_stacks(dev); + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void soc_init(void *data) +{ + printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); + fsp_silicon_init(false); +} + +static void soc_final(void *data) +{ + // Temp Fix - should be done by FSP, in 2S bios completion + // is not carried out on socket 2 + set_bios_init_completion(); +} + +static void soc_silicon_init_params(FSPS_UPD *silupd) +{ +} + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) +{ + const struct microcode *microcode_file; + size_t microcode_len; + + microcode_file = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, µcode_len); + + if ((microcode_file != NULL) && (microcode_len != 0)) { + /* Update CPU Microcode patch base address/size */ + silupd->FspsConfig.PcdCpuMicrocodePatchBase = + (uint32_t)microcode_file; + silupd->FspsConfig.PcdCpuMicrocodePatchSize = + (uint32_t)microcode_len; + } + + soc_silicon_init_params(silupd); + mainboard_silicon_init_params(silupd); +} + +struct chip_operations soc_intel_xeon_sp_ops = { + CHIP_NAME("Intel Xeon-SP SOC") + .enable_dev = soc_enable_dev, + .init = soc_init, + .final = soc_final +}; + +struct pci_operations soc_pci_ops = { + .set_subsystem = pci_dev_set_subsystem, +}; diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/chip.h new file mode 100644 index 0000000..72f2445 --- /dev/null +++ b/src/soc/intel/xeon_sp/chip.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_CHIP_H_ +#define _SOC_CHIP_H_ + +#include <stdint.h> +#include <intelblocks/cfg.h> +#include <soc/irq.h> + +struct soc_intel_xeon_sp_config { + /* Common struct containing soc config data required by common code */ + struct soc_intel_common_config common_soc_config; + + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + /** + * Device Interrupt Routing configuration + * Interrupt Pin x Route. + * 0h = PIRQA# + * 1h = PIRQB# + * 2h = PIRQC# + * 3h = PIRQD# + * 4h = PIRQE# + * 5h = PIRQF# + * 6h = PIRQG# + * 7h = PIRQH# + */ + uint16_t ir00_routing; + uint16_t ir01_routing; + uint16_t ir02_routing; + uint16_t ir03_routing; + uint16_t ir04_routing; + + /** + * Device Interrupt Polarity Control + * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC + */ + uint32_t ipc0; + uint32_t ipc1; + uint32_t ipc2; + uint32_t ipc3; + + uint64_t turbo_ratio_limit; + uint64_t turbo_ratio_limit_cores; + + uint32_t pstate_req_ratio; + + uint32_t vtd_support; + uint32_t coherency_support; + uint32_t ats_support; +}; + +extern struct chip_operations soc_intel_xeon_sp_ops; + +typedef struct soc_intel_xeon_sp_config config_t; + +#endif diff --git a/src/soc/intel/xeon_sp/cpu.c b/src/soc/intel/xeon_sp/cpu.c new file mode 100644 index 0000000..1d5c578 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpu.c @@ -0,0 +1,260 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <intelblocks/cpulib.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/mp.h> +#include <cpu/intel/turbo.h> +#include <soc/msr.h> +#include <soc/cpu.h> +#include <soc/soc_util.h> +#include <assert.h> +#include "chip.h" + +static const config_t *chip_config = NULL; + +static void xeon_configure_mca(void) +{ + msr_t msr; + struct cpuid_result cpuid_regs; + + /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE + * and CPUID.(EAX=1):EDX[14]==1 MCA*/ + cpuid_regs = cpuid(1); + if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14)) + return; + + msr = rdmsr(IA32_MCG_CAP); + if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { + /* Enable all error logging */ + msr.lo = msr.hi = 0xffffffff; + wrmsr(IA32_MCG_CTL, msr); + } + + /* TODO(adurbin): This should only be done on a cold boot. Also, some + of these banks are core vs package scope. For now every CPU clears + every bank. */ + mca_configure(); +} + +static void xeon_sp_core_init(struct device *cpu) +{ + msr_t msr; + + printk(BIOS_INFO, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", + __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); + assert(chip_config != NULL); + + /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/ + msr.hi = 0; + msr.lo = (PKG_CSTATE_NO_LIMIT | IO_MWAIT_REDIRECTION_ENABLE | CFG_LOCK_ENABLE); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); + + /* set MSR_PMG_IO_CAPTURE_BASE - scope per core */ + msr.hi = 0; + msr.lo = (LVL_2_BASE_ADDRESS | CST_RANGE_MAX_C6); + wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); + + /* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */ + msr = rdmsr(MSR_POWER_CTL); + msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE + | PROCHOT_LOCK_ENABLE); + wrmsr(MSR_POWER_CTL, msr); + + /* Set P-State ratio */ + msr = rdmsr(MSR_IA32_PERF_CTRL); + msr.lo &= ~PSTATE_REQ_MASK; + msr.lo |= (chip_config->pstate_req_ratio << PSTATE_REQ_SHIFT); + wrmsr(MSR_IA32_PERF_CTRL, msr); + + /* + * Set HWP base feature, EPP reg enumeration, lock thermal and msr + * TODO: Set LOCK_MISC_PWR_MGMT_MSR, Unexpected Exception if you + * lock & issue wrmsr on every thread + * This is package level MSR. Need to check if it updates correctly on + * multi-socket platform. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ + msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR | + LOCK_THERM_INT); + wrmsr(MSR_MISC_PWR_MGMT, msr); + } + + /* TODO MSR_VR_MISC_CONFIG */ + + /* Set current limit lock */ + msr = rdmsr(MSR_VR_CURRENT_CONFIG); + msr.lo |= CURRENT_LIMIT_LOCK; + wrmsr(MSR_VR_CURRENT_CONFIG, msr); + + /* Set Turbo Ratio Limits */ + msr.lo = chip_config->turbo_ratio_limit & 0xffffffff; + msr.hi = (chip_config->turbo_ratio_limit >> 32) & 0xffffffff; + wrmsr(MSR_TURBO_RATIO_LIMIT, msr); + + /* Set Turbo Ratio Limit Cores */ + msr.lo = chip_config->turbo_ratio_limit_cores & 0xffffffff; + msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff; + wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr); + + /* set Turbo Activation ratio */ + msr.hi = 0; + msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); + msr.lo |= MAX_NON_TURBO_RATIO; + wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); + + /* Enable Fast Strings */ + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= FAST_STRINGS_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); + + /* Set energy policy */ + msr_t msr1 = rdmsr(MSR_ENERGY_PERF_BIAS_CONFIG); + msr.lo = (msr1.lo & EPB_ENERGY_POLICY_MASK) >> EPB_ENERGY_POLICY_SHIFT; + msr.hi = 0; + wrmsr(MSR_IA32_ENERGY_PERF_BIAS, msr); + + /* Enable Turbo */ + enable_turbo(); + + /* Enable speed step. */ + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= SPEED_STEP_ENABLE_BIT; + wrmsr(IA32_MISC_ENABLE, msr); + } + + /* Clear out pending MCEs */ + xeon_configure_mca(); +} + +static struct device_operations cpu_dev_ops = { + .init = xeon_sp_core_init, +}; + +static const struct cpu_device_id cpu_table[] = { + /* Skylake-SP A0/A1 CPUID 0x506f0*/ + {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_A0_A1}, + /* Skylake-SP B0 CPUID 0x506f1*/ + {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_B0}, + /* Skylake-SP 4 CPUID 0x50654*/ + {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_4}, + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +static void set_max_turbo_freq(void) +{ + msr_t msr, perf_ctl; + + FUNC_ENTER(); + perf_ctl.hi = 0; + + /* Check for configurable TDP option */ + if (get_turbo_state() == TURBO_ENABLED) { + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else if (cpu_config_tdp_levels()) { + /* Set to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + perf_ctl.lo = (msr.lo & 0xff) << 8; + } else { + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + perf_ctl.lo = msr.lo & 0xff00; + } + wrmsr(IA32_PERF_CTL, perf_ctl); + + printk(BIOS_DEBUG, "cpu: frequency set to %d\n", + ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + FUNC_EXIT(); +} + +/* + * Do essential initialization tasks before APs can be fired up + * + * Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This + * creates the MTRR solution that the APs will use. Otherwise APs will try to + * apply the incomplete solution as the BSP is calculating it. + */ +static void pre_mp_init(void) +{ + printk(BIOS_DEBUG, "%s: entry\n", __func__); + + x86_setup_fixed_mtrrs(); +} + +static void post_mp_init(void) +{ + /* Set Max Ratio */ + set_max_turbo_freq(); + + /* + * TODO: Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + */ +} + +/* + * CPU initialization recipe + * + * Note that no microcode update is passed to the init function. CSE updates + * the microcode on all cores before releasing them from reset. That means that + * the BSP and all APs will come up with the same microcode revision. + */ +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_platform_thread_count, + //.get_smm_info = get_smm_info, /* TODO */ + .get_smm_info = NULL, + //.pre_mp_smm_init = southcluster_smm_clear_state, /* TODO */ + .pre_mp_smm_init = NULL, + //.relocation_handler = relocation_handler, /* TODO */ + .relocation_handler = NULL, + .post_mp_init = post_mp_init, +}; + + +void xeon_sp_init_cpus(struct device *dev) +{ + FUNC_ENTER(); + + /* + * This gets used in cpu device callback. Other than cpu 0, + * rest of the CPU devices do not have + * chip_info updated. Global chip_config is used as workaround + */ + chip_config = dev->chip_info; + + config_reset_cpl3_csrs(); + + /* calls src/cpu/x86/mp_init.c */ + if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); + + /* update numa domain for all cpu devices */ + xeonsp_init_cpu_config(); + + FUNC_EXIT(); +} diff --git a/src/soc/intel/xeon_sp/hob_display.c b/src/soc/intel/xeon_sp/hob_display.c new file mode 100644 index 0000000..1508011 --- /dev/null +++ b/src/soc/intel/xeon_sp/hob_display.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> +#include <assert.h> +#include <hob_iiouds.h> +#include <hob_memmap.h> + +static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; +static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + +struct guid_name_map { + const void *guid; + const char *name; +}; + +static const struct guid_name_map guid_names[] = { + { fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID" }, + { fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID" }, +}; + +const char *soc_get_guid_name(const uint8_t *guid) +{ + size_t index; + + /* Compare the GUID values in this module */ + for (index = 0; index < ARRAY_SIZE(guid_names); index++) + if (fsp_guid_compare(guid, guid_names[index].guid)) + return guid_names[index].name; + + return NULL; +} + +void soc_display_hob(const struct hob_header *hob) +{ + const struct hob_resource *res; + + res = fsp_hob_header_to_resource(hob); + assert(res != NULL); + printk(BIOS_DEBUG, "\tResource type: 0x%x, attribute: 0x%x, addr: 0x%08llx, len: 0x%08llx\n", + res->type, res->attribute_type, res->addr, res->length); + printk(BIOS_DEBUG, "\tOwner GUID: "); + fsp_print_guid(res->owner_guid); + printk(BIOS_DEBUG, " (%s)\n", fsp_get_guid_name(res->owner_guid)); + + if (fsp_guid_compare(res->owner_guid, fsp_hob_iio_uds_guid) == 0) + soc_display_iio_universal_data_hob(); + else if (fsp_guid_compare(res->owner_guid, fsp_hob_memmap_guid) == 0) + soc_display_memmap_hob(); + else + hexdump(hob, hob->length); +} + +void soc_display_memmap_hob(void) +{ + size_t hob_size = 0; + const struct SystemMemoryMapHob *hob = + fsp_find_extension_hob_by_guid(fsp_hob_memmap_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + printk(BIOS_DEBUG, "===================== MEMORY MAP HOB DATA =====================\n"); + printk(BIOS_DEBUG, "hob: %p, hob_size: 0x%lx, SystemMemoryMapHob size: 0x%lx, " + "MAX_SOCKET: %d, SAD_RULES: %d\n", + hob, hob_size, sizeof(struct SystemMemoryMapHob), MAX_SOCKET, SAD_RULES); + printk(BIOS_DEBUG, "\tlowMemBase: 0x%x, lowMemSize: 0x%x, highMemBase: 0x%x, " + "highMemSize: 0x%x\n", + hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize); + printk(BIOS_DEBUG, "\tasilLoMemBase: 0x%x, asilHiMemBase: 0x%x, asilLoMemSize: 0x%x, " + "asilHiMemSize: 0x%x\n", + hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize); + printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x, memMode: 0x%x, volMemMode: 0x%x, " + "DimmType: 0x%x, DramType: 0x%x\n", + hob->memSize, hob->memFreq, hob->memMode, hob->volMemMode, + hob->DimmType, hob->DramType); + printk(BIOS_DEBUG, "\tNumChPerMC: 0x%x, numberEntries: 0x%x, maxIMC: 0x%x, maxCh: 0x%x\n", + hob->NumChPerMC, hob->numberEntries, hob->maxIMC, hob->maxCh); + + printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d\n", hob->numberEntries); + for (int e = 0; e < hob->numberEntries; ++e) { + const struct SystemMemoryMapElement *mem_element = &hob->Element[e]; + printk(BIOS_DEBUG, "\t\tmemory_map %d BaseAddress: 0x%x, ElementSize: 0x%x, Type: 0x%x\n", + e, mem_element->BaseAddress, + mem_element->ElementSize, mem_element->Type); + } +} + +void soc_display_iio_universal_data_hob(void) +{ + size_t hob_size = 0; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_uds_guid, &hob_size); + + assert(hob != NULL && hob_size != 0); + + printk(BIOS_DEBUG, "===================== IIO_UDS HOB DATA =====================\n"); + + printk(BIOS_DEBUG, "\t===================== SYSTEM STATUS =====================\n"); + printk(BIOS_DEBUG, "\tcpuType: 0x%x\n", hob->SystemStatus.cpuType); + printk(BIOS_DEBUG, "\tcpuSubType: 0x%x\n", hob->SystemStatus.cpuSubType); + printk(BIOS_DEBUG, "\tSystemRasType: 0x%x\n", hob->SystemStatus.SystemRasType); + printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus); + for (int x = 0; x < MAX_SOCKET; ++x) { + printk(BIOS_DEBUG, "\tSocket %d FusedCores: 0x%x, ActiveCores: 0x%x, " + "MaxCoreToBusRatio: 0x%x, MinCoreToBusRatio: 0x%x\n", + x, hob->SystemStatus.FusedCores[x], hob->SystemStatus.ActiveCores[x], + hob->SystemStatus.MaxCoreToBusRatio[x], + hob->SystemStatus.MinCoreToBusRatio[x]); + } + printk(BIOS_DEBUG, "\tCurrentCoreToBusRatio: 0x%x\n", + hob->SystemStatus.CurrentCoreToBusRatio); + printk(BIOS_DEBUG, "\tIntelSpeedSelectCapable: 0x%x\n", + hob->SystemStatus.IntelSpeedSelectCapable); + printk(BIOS_DEBUG, "\tIssConfigTdpLevelInfo: 0x%x\n", + hob->SystemStatus.IssConfigTdpLevelInfo); + for (int x = 0; x < TDP_MAX_LEVEL; ++x) { + printk(BIOS_DEBUG, "\t\tTDL Level %d IssConfigTdpTdpInfo: 0x%x, " + "IssConfigTdpPowerInfo: 0x%x, IssConfigTdpCoreCount: 0x%x\n", + x, hob->SystemStatus.IssConfigTdpTdpInfo[x], + hob->SystemStatus.IssConfigTdpPowerInfo[x], + hob->SystemStatus.IssConfigTdpCoreCount[x]); + } + printk(BIOS_DEBUG, "\tsocketPresentBitMap: 0x%x\n", + hob->SystemStatus.socketPresentBitMap); + printk(BIOS_DEBUG, "\ttolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit); + printk(BIOS_DEBUG, "\ttohmLimit: 0x%x\n", hob->SystemStatus.tohmLimit); + printk(BIOS_DEBUG, "\tmmCfgBase: 0x%x\n", hob->SystemStatus.mmCfgBase); + printk(BIOS_DEBUG, "\tnumChPerMC: 0x%x\n", hob->SystemStatus.numChPerMC); + printk(BIOS_DEBUG, "\tmaxCh: 0x%x\n", hob->SystemStatus.maxCh); + printk(BIOS_DEBUG, "\tmaxIMC: 0x%x\n", hob->SystemStatus.maxIMC); + + printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n"); + printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase); + printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit); + printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n", + hob->PlatformData.PlatGlobalMmiolBase); + printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n", + hob->PlatformData.PlatGlobalMmiolLimit); + printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n", + hob->PlatformData.PlatGlobalMmiohBase); + printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n", + hob->PlatformData.PlatGlobalMmiohLimit); + printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize); + printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize); + printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase); + printk(BIOS_DEBUG, "\tPciExpressSize: 0x%x\n", hob->PlatformData.PciExpressSize); + printk(BIOS_DEBUG, "\tMemTolm: 0x%x\n", hob->PlatformData.MemTolm); + printk(BIOS_DEBUG, "\tnumofIIO: 0x%x\n", hob->PlatformData.numofIIO); + printk(BIOS_DEBUG, "\tMaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber); + printk(BIOS_DEBUG, "\tIoGranularity: 0x%x\n", hob->PlatformData.IoGranularity); + printk(BIOS_DEBUG, "\tMmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity); + printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n", + hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo); + + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + printk(BIOS_DEBUG, "\t============ Socket %d Info ================\n", s); + printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", + hob->PlatformData.IIO_resource[s].SocketID); + printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", + hob->PlatformData.IIO_resource[s].BusBase); + printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", + hob->PlatformData.IIO_resource[s].BusLimit); + printk(BIOS_DEBUG, "\tPciResourceIoBase: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceIoBase); + printk(BIOS_DEBUG, "\tPciResourceIoLimit: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceIoLimit); + printk(BIOS_DEBUG, "\tIoApicBase: 0x%x\n", + hob->PlatformData.IIO_resource[s].IoApicBase); + printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n", + hob->PlatformData.IIO_resource[s].IoApicLimit); + printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceMem32Base); + printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n", + hob->PlatformData.IIO_resource[s].PciResourceMem32Limit); + printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n", + hob->PlatformData.IIO_resource[s].PciResourceMem64Base); + printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n", + hob->PlatformData.IIO_resource[s].PciResourceMem64Limit); + + printk(BIOS_DEBUG, "\t============ Stack Info ================\n"); + for (int x = 0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + printk(BIOS_DEBUG, "\t\t========== Stack %d ===============\n", x); + printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase); + printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit); + printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", + ri->PciResourceIoBase); + printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", + ri->PciResourceIoLimit); + printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase); + printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit); + printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n", + ri->PciResourceMem32Base); + printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n", + ri->PciResourceMem32Limit); + printk(BIOS_DEBUG, "\t\tPciResourceMem64Base: 0x%llx\n", + ri->PciResourceMem64Base); + printk(BIOS_DEBUG, "\t\tPciResourceMem64Limit: 0x%llx\n", + ri->PciResourceMem64Limit); + printk(BIOS_DEBUG, "\t\tVtdBarAddress: 0x%x\n", ri->VtdBarAddress); + } + + printk(BIOS_DEBUG, "\t============ PcieInfo ================\n"); + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[s]; + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n", + p, iio_resource.PcieInfo.PortInfo[p].Device, + iio_resource.PcieInfo.PortInfo[p].Function); + } + } + + printk(BIOS_DEBUG, "\t============ Bus Bases ===============\n"); + for (int socket = 0; socket < MAX_SOCKET; ++socket) { + for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { + printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", + socket, stack, + hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]); + } + } +} diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h new file mode 100644 index 0000000..641a3c5 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_ACPI_H_ +#define _SOC_ACPI_H_ + +#include <arch/acpi.h> +#include <soc/nvs.h> + +#define MEM_BLK_COUNT 0x140 +typedef struct { + uint8_t buf[32]; +} MEM_BLK; + +void acpi_create_serialio_ssdt(acpi_header_t *ssdt); +unsigned long acpi_madt_irq_overrides(unsigned long current); +void acpi_init_gnvs(global_nvs_t *gnvs); +unsigned long northbridge_write_acpi_tables(struct device *device, + unsigned long current, struct acpi_rsdp *rsdp); +void uncore_inject_dsdt(void); +void motherboard_fill_fadt(acpi_fadt_t *fadt); + +#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/cpu.h b/src/soc/intel/xeon_sp/include/soc/cpu.h new file mode 100644 index 0000000..82b893c --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/cpu.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CPU_H_ +#define _SOC_CPU_H_ + +#include <device/device.h> + +/* SKXSP CPUID */ +#define CPUID_SKYLAKE_SP_A0_A1 0x506f0 +#define CPUID_SKYLAKE_SP_B0 0x506f1 +#define CPUID_SKYLAKE_SP_4 0x50654 + +/* CPU bus clock is fixed at 100MHz */ +#define CPU_BCLK 100 + +int get_cpu_count(void); +void xeon_sp_init_cpus(struct device *dev); + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h new file mode 100644 index 0000000..8cb472d --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_SOC_DEFS_H_ +#define _GPIO_SOC_DEFS_H_ + +/// +/// Skylake-SP chipset GPIO Groups +/// +#define GPIO_SKL_H_GROUP_GPP_A 0x0100 +#define GPIO_SKL_H_GROUP_GPP_B 0x0101 +#define GPIO_SKL_H_GROUP_GPP_C 0x0102 +#define GPIO_SKL_H_GROUP_GPP_D 0x0103 +#define GPIO_SKL_H_GROUP_GPP_E 0x0104 +#define GPIO_SKL_H_GROUP_GPP_F 0x0105 +#define GPIO_SKL_H_GROUP_GPP_G 0x0106 +#define GPIO_SKL_H_GROUP_GPP_H 0x0107 +#define GPIO_SKL_H_GROUP_GPP_I 0x0108 +#define GPIO_SKL_H_GROUP_GPP_J 0x0109 +#define GPIO_SKL_H_GROUP_GPP_K 0x010A +#define GPIO_SKL_H_GROUP_GPP_L 0x010B +#define GPIO_SKL_H_GROUP_GPD 0x010C + +/// +/// SKL H GPIO pins +/// +#define GPIO_SKL_H_GPP_A0 0x01000000 +#define GPIO_SKL_H_GPP_A1 0x01000001 +#define GPIO_SKL_H_GPP_A2 0x01000002 +#define GPIO_SKL_H_GPP_A3 0x01000003 +#define GPIO_SKL_H_GPP_A4 0x01000004 +#define GPIO_SKL_H_GPP_A5 0x01000005 +#define GPIO_SKL_H_GPP_A6 0x01000006 +#define GPIO_SKL_H_GPP_A7 0x01000007 +#define GPIO_SKL_H_GPP_A8 0x01000008 +#define GPIO_SKL_H_GPP_A9 0x01000009 +#define GPIO_SKL_H_GPP_A10 0x0100000A +#define GPIO_SKL_H_GPP_A11 0x0100000B +#define GPIO_SKL_H_GPP_A12 0x0100000C +#define GPIO_SKL_H_GPP_A13 0x0100000D +#define GPIO_SKL_H_GPP_A14 0x0100000E +#define GPIO_SKL_H_GPP_A15 0x0100000F +#define GPIO_SKL_H_GPP_A16 0x01000010 +#define GPIO_SKL_H_GPP_A17 0x01000011 +#define GPIO_SKL_H_GPP_A18 0x01000012 +#define GPIO_SKL_H_GPP_A19 0x01000013 +#define GPIO_SKL_H_GPP_A20 0x01000014 +#define GPIO_SKL_H_GPP_A21 0x01000015 +#define GPIO_SKL_H_GPP_A22 0x01000016 +#define GPIO_SKL_H_GPP_A23 0x01000017 +#define GPIO_SKL_H_GPP_B0 0x01010000 +#define GPIO_SKL_H_GPP_B1 0x01010001 +#define GPIO_SKL_H_GPP_B2 0x01010002 +#define GPIO_SKL_H_GPP_B3 0x01010003 +#define GPIO_SKL_H_GPP_B4 0x01010004 +#define GPIO_SKL_H_GPP_B5 0x01010005 +#define GPIO_SKL_H_GPP_B6 0x01010006 +#define GPIO_SKL_H_GPP_B7 0x01010007 +#define GPIO_SKL_H_GPP_B8 0x01010008 +#define GPIO_SKL_H_GPP_B9 0x01010009 +#define GPIO_SKL_H_GPP_B10 0x0101000A +#define GPIO_SKL_H_GPP_B11 0x0101000B +#define GPIO_SKL_H_GPP_B12 0x0101000C +#define GPIO_SKL_H_GPP_B13 0x0101000D +#define GPIO_SKL_H_GPP_B14 0x0101000E +#define GPIO_SKL_H_GPP_B15 0x0101000F +#define GPIO_SKL_H_GPP_B16 0x01010010 +#define GPIO_SKL_H_GPP_B17 0x01010011 +#define GPIO_SKL_H_GPP_B18 0x01010012 +#define GPIO_SKL_H_GPP_B19 0x01010013 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define GPIO_SKL_H_GPP_B21 0x01010015 +#define GPIO_SKL_H_GPP_B22 0x01010016 +#define GPIO_SKL_H_GPP_B23 0x01010017 +#define GPIO_SKL_H_GPP_C0 0x01020000 +#define GPIO_SKL_H_GPP_C1 0x01020001 +#define GPIO_SKL_H_GPP_C2 0x01020002 +#define GPIO_SKL_H_GPP_C3 0x01020003 +#define GPIO_SKL_H_GPP_C4 0x01020004 +#define GPIO_SKL_H_GPP_C5 0x01020005 +#define GPIO_SKL_H_GPP_C6 0x01020006 +#define GPIO_SKL_H_GPP_C7 0x01020007 +#define GPIO_SKL_H_GPP_C8 0x01020008 +#define GPIO_SKL_H_GPP_C9 0x01020009 +#define GPIO_SKL_H_GPP_C10 0x0102000A +#define GPIO_SKL_H_GPP_C11 0x0102000B +#define GPIO_SKL_H_GPP_C12 0x0102000C +#define GPIO_SKL_H_GPP_C13 0x0102000D +#define GPIO_SKL_H_GPP_C14 0x0102000E +#define GPIO_SKL_H_GPP_C15 0x0102000F +#define GPIO_SKL_H_GPP_C16 0x01020010 +#define GPIO_SKL_H_GPP_C17 0x01020011 +#define GPIO_SKL_H_GPP_C18 0x01020012 +#define GPIO_SKL_H_GPP_C19 0x01020013 +#define GPIO_SKL_H_GPP_C20 0x01020014 +#define GPIO_SKL_H_GPP_C21 0x01020015 +#define GPIO_SKL_H_GPP_C22 0x01020016 +#define GPIO_SKL_H_GPP_C23 0x01020017 +#define GPIO_SKL_H_GPP_D0 0x01030000 +#define GPIO_SKL_H_GPP_D1 0x01030001 +#define GPIO_SKL_H_GPP_D2 0x01030002 +#define GPIO_SKL_H_GPP_D3 0x01030003 +#define GPIO_SKL_H_GPP_D4 0x01030004 +#define GPIO_SKL_H_GPP_D5 0x01030005 +#define GPIO_SKL_H_GPP_D6 0x01030006 +#define GPIO_SKL_H_GPP_D7 0x01030007 +#define GPIO_SKL_H_GPP_D8 0x01030008 +#define GPIO_SKL_H_GPP_D9 0x01030009 +#define GPIO_SKL_H_GPP_D10 0x0103000A +#define GPIO_SKL_H_GPP_D11 0x0103000B +#define GPIO_SKL_H_GPP_D12 0x0103000C +#define GPIO_SKL_H_GPP_D13 0x0103000D +#define GPIO_SKL_H_GPP_D14 0x0103000E +#define GPIO_SKL_H_GPP_D15 0x0103000F +#define GPIO_SKL_H_GPP_D16 0x01030010 +#define GPIO_SKL_H_GPP_D17 0x01030011 +#define GPIO_SKL_H_GPP_D18 0x01030012 +#define GPIO_SKL_H_GPP_D19 0x01030013 +#define GPIO_SKL_H_GPP_D20 0x01030014 +#define GPIO_SKL_H_GPP_D21 0x01030015 +#define GPIO_SKL_H_GPP_D22 0x01030016 +#define GPIO_SKL_H_GPP_D23 0x01030017 +#define GPIO_SKL_H_GPP_E0 0x01040000 +#define GPIO_SKL_H_GPP_E1 0x01040001 +#define GPIO_SKL_H_GPP_E2 0x01040002 +#define GPIO_SKL_H_GPP_E3 0x01040003 +#define GPIO_SKL_H_GPP_E4 0x01040004 +#define GPIO_SKL_H_GPP_E5 0x01040005 +#define GPIO_SKL_H_GPP_E6 0x01040006 +#define GPIO_SKL_H_GPP_E7 0x01040007 +#define GPIO_SKL_H_GPP_E8 0x01040008 +#define GPIO_SKL_H_GPP_E9 0x01040009 +#define GPIO_SKL_H_GPP_E10 0x0104000A +#define GPIO_SKL_H_GPP_E11 0x0104000B +#define GPIO_SKL_H_GPP_E12 0x0104000C +#define GPIO_SKL_H_GPP_F0 0x01050000 +#define GPIO_SKL_H_GPP_F1 0x01050001 +#define GPIO_SKL_H_GPP_F2 0x01050002 +#define GPIO_SKL_H_GPP_F3 0x01050003 +#define GPIO_SKL_H_GPP_F4 0x01050004 +#define GPIO_SKL_H_GPP_F5 0x01050005 +#define GPIO_SKL_H_GPP_F6 0x01050006 +#define GPIO_SKL_H_GPP_F7 0x01050007 +#define GPIO_SKL_H_GPP_F8 0x01050008 +#define GPIO_SKL_H_GPP_F9 0x01050009 +#define GPIO_SKL_H_GPP_F10 0x0105000A +#define GPIO_SKL_H_GPP_F11 0x0105000B +#define GPIO_SKL_H_GPP_F12 0x0105000C +#define GPIO_SKL_H_GPP_F13 0x0105000D +#define GPIO_SKL_H_GPP_F14 0x0105000E +#define GPIO_SKL_H_GPP_F15 0x0105000F +#define GPIO_SKL_H_GPP_F16 0x01050010 +#define GPIO_SKL_H_GPP_F17 0x01050011 +#define GPIO_SKL_H_GPP_F18 0x01050012 +#define GPIO_SKL_H_GPP_F19 0x01050013 +#define GPIO_SKL_H_GPP_F20 0x01050014 +#define GPIO_SKL_H_GPP_F21 0x01050015 +#define GPIO_SKL_H_GPP_F22 0x01050016 +#define GPIO_SKL_H_GPP_F23 0x01050017 +#define GPIO_SKL_H_GPP_G0 0x01060000 +#define GPIO_SKL_H_GPP_G1 0x01060001 +#define GPIO_SKL_H_GPP_G2 0x01060002 +#define GPIO_SKL_H_GPP_G3 0x01060003 +#define GPIO_SKL_H_GPP_G4 0x01060004 +#define GPIO_SKL_H_GPP_G5 0x01060005 +#define GPIO_SKL_H_GPP_G6 0x01060006 +#define GPIO_SKL_H_GPP_G7 0x01060007 +#define GPIO_SKL_H_GPP_G8 0x01060008 +#define GPIO_SKL_H_GPP_G9 0x01060009 +#define GPIO_SKL_H_GPP_G10 0x0106000A +#define GPIO_SKL_H_GPP_G11 0x0106000B +#define GPIO_SKL_H_GPP_G12 0x0106000C +#define GPIO_SKL_H_GPP_G13 0x0106000D +#define GPIO_SKL_H_GPP_G14 0x0106000E +#define GPIO_SKL_H_GPP_G15 0x0106000F +#define GPIO_SKL_H_GPP_G16 0x01060010 +#define GPIO_SKL_H_GPP_G17 0x01060011 +#define GPIO_SKL_H_GPP_G18 0x01060012 +#define GPIO_SKL_H_GPP_G19 0x01060013 +#define GPIO_SKL_H_GPP_G20 0x01060014 +#define GPIO_SKL_H_GPP_G21 0x01060015 +#define GPIO_SKL_H_GPP_G22 0x01060016 +#define GPIO_SKL_H_GPP_G23 0x01060017 +#define GPIO_SKL_H_GPP_H0 0x01070000 +#define GPIO_SKL_H_GPP_H1 0x01070001 +#define GPIO_SKL_H_GPP_H2 0x01070002 +#define GPIO_SKL_H_GPP_H3 0x01070003 +#define GPIO_SKL_H_GPP_H4 0x01070004 +#define GPIO_SKL_H_GPP_H5 0x01070005 +#define GPIO_SKL_H_GPP_H6 0x01070006 +#define GPIO_SKL_H_GPP_H7 0x01070007 +#define GPIO_SKL_H_GPP_H8 0x01070008 +#define GPIO_SKL_H_GPP_H9 0x01070009 +#define GPIO_SKL_H_GPP_H10 0x0107000A +#define GPIO_SKL_H_GPP_H11 0x0107000B +#define GPIO_SKL_H_GPP_H12 0x0107000C +#define GPIO_SKL_H_GPP_H13 0x0107000D +#define GPIO_SKL_H_GPP_H14 0x0107000E +#define GPIO_SKL_H_GPP_H15 0x0107000F +#define GPIO_SKL_H_GPP_H16 0x01070010 +#define GPIO_SKL_H_GPP_H17 0x01070011 +#define GPIO_SKL_H_GPP_H18 0x01070012 +#define GPIO_SKL_H_GPP_H19 0x01070013 +#define GPIO_SKL_H_GPP_H20 0x01070014 +#define GPIO_SKL_H_GPP_H21 0x01070015 +#define GPIO_SKL_H_GPP_H22 0x01070016 +#define GPIO_SKL_H_GPP_H23 0x01070017 +#define GPIO_SKL_H_GPP_I0 0x01080000 +#define GPIO_SKL_H_GPP_I1 0x01080001 +#define GPIO_SKL_H_GPP_I2 0x01080002 +#define GPIO_SKL_H_GPP_I3 0x01080003 +#define GPIO_SKL_H_GPP_I4 0x01080004 +#define GPIO_SKL_H_GPP_I5 0x01080005 +#define GPIO_SKL_H_GPP_I6 0x01080006 +#define GPIO_SKL_H_GPP_I7 0x01080007 +#define GPIO_SKL_H_GPP_I8 0x01080008 +#define GPIO_SKL_H_GPP_I9 0x01080009 +#define GPIO_SKL_H_GPP_I10 0x0108000A + +#define GPIO_SKL_H_GPP_J0 0x01090000 +#define GPIO_SKL_H_GPP_J1 0x01090001 +#define GPIO_SKL_H_GPP_J2 0x01090002 +#define GPIO_SKL_H_GPP_J3 0x01090003 +#define GPIO_SKL_H_GPP_J4 0x01090004 +#define GPIO_SKL_H_GPP_J5 0x01090005 +#define GPIO_SKL_H_GPP_J6 0x01090006 +#define GPIO_SKL_H_GPP_J7 0x01090007 +#define GPIO_SKL_H_GPP_J8 0x01090008 +#define GPIO_SKL_H_GPP_J9 0x01090009 +#define GPIO_SKL_H_GPP_J10 0x0109000A +#define GPIO_SKL_H_GPP_J11 0x0109000B +#define GPIO_SKL_H_GPP_J12 0x0109000C +#define GPIO_SKL_H_GPP_J13 0x0109000D +#define GPIO_SKL_H_GPP_J14 0x0109000E +#define GPIO_SKL_H_GPP_J15 0x0109000F +#define GPIO_SKL_H_GPP_J16 0x01090010 +#define GPIO_SKL_H_GPP_J17 0x01090011 +#define GPIO_SKL_H_GPP_J18 0x01090012 +#define GPIO_SKL_H_GPP_J19 0x01090013 +#define GPIO_SKL_H_GPP_J20 0x01090014 +#define GPIO_SKL_H_GPP_J21 0x01090015 +#define GPIO_SKL_H_GPP_J22 0x01090016 +#define GPIO_SKL_H_GPP_J23 0x01090017 +#define GPIO_SKL_H_GPP_K0 0x010A0000 +#define GPIO_SKL_H_GPP_K1 0x010A0001 +#define GPIO_SKL_H_GPP_K2 0x010A0002 +#define GPIO_SKL_H_GPP_K3 0x010A0003 +#define GPIO_SKL_H_GPP_K4 0x010A0004 +#define GPIO_SKL_H_GPP_K5 0x010A0005 +#define GPIO_SKL_H_GPP_K6 0x010A0006 +#define GPIO_SKL_H_GPP_K7 0x010A0007 +#define GPIO_SKL_H_GPP_K8 0x010A0008 +#define GPIO_SKL_H_GPP_K9 0x010A0009 +#define GPIO_SKL_H_GPP_K10 0x010A000A +#define GPIO_SKL_H_GPP_L2 0x010B0002 +#define GPIO_SKL_H_GPP_L3 0x010B0003 +#define GPIO_SKL_H_GPP_L4 0x010B0004 +#define GPIO_SKL_H_GPP_L5 0x010B0005 +#define GPIO_SKL_H_GPP_L6 0x010B0006 +#define GPIO_SKL_H_GPP_L7 0x010B0007 +#define GPIO_SKL_H_GPP_L8 0x010B0008 +#define GPIO_SKL_H_GPP_L9 0x010B0009 +#define GPIO_SKL_H_GPP_L10 0x010B000A +#define GPIO_SKL_H_GPP_L11 0x010B000B +#define GPIO_SKL_H_GPP_L12 0x010B000C +#define GPIO_SKL_H_GPP_L13 0x010B000D +#define GPIO_SKL_H_GPP_L14 0x010B000E +#define GPIO_SKL_H_GPP_L15 0x010B000F +#define GPIO_SKL_H_GPP_L16 0x010B0010 +#define GPIO_SKL_H_GPP_L17 0x010B0011 +#define GPIO_SKL_H_GPP_L18 0x010B0012 +#define GPIO_SKL_H_GPP_L19 0x010B0013 +#define GPIO_SKL_H_GPD0 0x010C0000 +#define GPIO_SKL_H_GPD1 0x010C0001 +#define GPIO_SKL_H_GPD2 0x010C0002 +#define GPIO_SKL_H_GPD3 0x010C0003 +#define GPIO_SKL_H_GPD4 0x010C0004 +#define GPIO_SKL_H_GPD5 0x010C0005 +#define GPIO_SKL_H_GPD6 0x010C0006 +#define GPIO_SKL_H_GPD7 0x010C0007 +#define GPIO_SKL_H_GPD8 0x010C0008 +#define GPIO_SKL_H_GPD9 0x010C0009 +#define GPIO_SKL_H_GPD10 0x010C000A +#define GPIO_SKL_H_GPD11 0x010C000B + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h new file mode 100644 index 0000000..7c825a4 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_IOMAP_H_ +#define _SOC_IOMAP_H_ + +#define MAP_ENTRY(reg_, is_64_, is_limit_, mask_bits_, desc_) \ + { \ + .reg = reg_, .is_64_bit = is_64_, .is_limit = is_limit_, \ + .mask_bits = mask_bits_, .description = desc_, \ + } + +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 1, 1, mask_bits_, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 0, desc_) +#define MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_) + +// SPI BAR0 MMIO base address +#define SPI_BASE_ADDRESS 0xfe010000 +#define SPI_BASE_SIZE 0x1000 + +#define ACPI_BASE_ADDRESS 0x500 + +/* Video RAM */ +#define VGA_BASE_ADDRESS 0xa0000 +#define VGA_BASE_SIZE 0x20000 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 + +#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS + +#endif /* _SOC_IOMAP_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/irq.h b/src/soc/intel/xeon_sp/include/soc/irq.h new file mode 100644 index 0000000..06942ae --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/irq.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_IRQ_H_ +#define _SOC_IRQ_H_ + +#define PCH_IRQ10 10 +#define PCH_IRQ11 11 + +#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h new file mode 100644 index 0000000..6004490 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MSR_H_ +#define _SOC_MSR_H_ + +#include <intelblocks/msr.h> + +#define IA32_MCG_CAP 0x179 +#define IA32_MCG_CAP_COUNT_MASK 0xff +#define IA32_MCG_CAP_CTL_P_BIT 8 +#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT) + +#define IA32_MCG_CTL 0x17b + +/* IA32_MISC_ENABLE bits */ +#define FAST_STRINGS_ENABLE_BIT (1 << 0) +#define SPEED_STEP_ENABLE_BIT (1 << 16) +#define MONIOR_ENABLE_BIT (1 << 18) + +#define MSR_IA32_ENERGY_PERF_BIAS 0x1b0 + +/* MSR_PKG_CST_CONFIG_CONTROL bits */ +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 +#define PKG_CSTATE_LIMIT_SHIFT 0 /* 0:3 */ +/* No package C-state limit. All C-States supported by the processor are available. */ +#define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT) +#define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT) +#define IO_MWAIT_REDIRECTION_SHIFT 10 +#define IO_MWAIT_REDIRECTION_ENABLE (1 << IO_MWAIT_REDIRECTION_SHIFT) +#define CFG_LOCK_SHIFT 15 +#define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT) + +/* MSR_PMG_IO_CAPTURE_BASE bits */ +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define LVL_2_BASE_ADDRESS_SHIFT 0 /* 15:0 bits */ +#define LVL_2_BASE_ADDRESS (0x0514 << LVL_2_BASE_ADDRESS_SHIFT) +#define CST_RANGE_SHIFT 16 /* 18:16 bits */ +#define CST_RANGE_MAX_C6 (0x1 << CST_RANGE_SHIFT) + +/* MSR_POWER_CTL bits */ +#define MSR_POWER_CTL 0x1fc +#define BIDIR_PROCHOT_ENABLE_SHIFT 0 +#define BIDIR_PROCHOT_ENABLE (1 << BIDIR_PROCHOT_ENABLE_SHIFT) +#define FAST_BRK_SNP_ENABLE_SHIFT 3 +#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT) +#define FAST_BRK_INT_ENABLE_SHIFT 4 +#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT) +#define PHOLD_CST_PREVENTION_INIT_SHIFT 6 +#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT) +#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18 +#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT) +#define PROCHOT_OUTPUT_DISABLE_SHIFT 21 +#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT) +#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24 +#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT) +#define PROCHOT_LOCK_SHIFT 27 +#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT) +#define LTR_IIO_DISABLE_SHIFT 29 +#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT) + +/* MSR_IA32_PERF_CTRL (0x199) bits */ +#define MSR_IA32_PERF_CTRL 0x199 +#define PSTATE_REQ_SHIFT 8 /* 8:14 bits */ +#define PSTATE_REQ_MASK (0x7f << PSTATE_REQ_SHIFT) +#define PSTATE_REQ_RATIO (0xa << PSTATE_REQ_SHIFT) + +/* MSR_MISC_PWR_MGMT bits */ +#define MSR_MISC_PWR_MGMT 0x1aa +#define HWP_ENUM_SHIFT 6 +#define HWP_ENUM_ENABLE (1 << HWP_ENUM_SHIFT) +#define HWP_EPP_SHIFT 12 +#define HWP_EPP_ENUM_ENABLE (1 << HWP_EPP_SHIFT) +#define LOCK_MISC_PWR_MGMT_MSR_SHIFT 13 +#define LOCK_MISC_PWR_MGMT_MSR (1 << LOCK_MISC_PWR_MGMT_MSR_SHIFT) +#define LOCK_THERM_INT_SHIFT 22 +#define LOCK_THERM_INT (1 << LOCK_THERM_INT_SHIFT) + +/* MSR_TURBO_RATIO_LIMIT bits */ +#define MSR_TURBO_RATIO_LIMIT 0x1ad + +/* MSR_TURBO_RATIO_LIMIT_CORES (0x1ae) */ +#define MSR_TURBO_RATIO_LIMIT_CORES 0x1ae + +/* MSR_VR_CURRENT_CONFIG bits */ +#define MSR_VR_CURRENT_CONFIG 0x601 +#define CURRENT_LIMIT_LOCK_SHIFT 31 +#define CURRENT_LIMIT_LOCK (0x1 << CURRENT_LIMIT_LOCK_SHIFT) + +/* MSR_TURBO_ACTIVATION_RATIO bits */ +#define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define MAX_NON_TURBO_RATIO_SHIFT 0 +#define MAX_NON_TURBO_RATIO (0xff << MAX_NON_TURBO_RATIO_SHIFT) + +/* MSR_ENERGY_PERF_BIAS_CONFIG bits */ +#define MSR_ENERGY_PERF_BIAS_CONFIG 0xa01 +#define EPB_ENERGY_POLICY_SHIFT 3 +#define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT) + +#endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h new file mode 100644 index 0000000..00dded3 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/nvs.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 - 2009 coresystems GmbH + * Copyright (C) 2011 Google Inc + * Copyright (C) 2014 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _SOC_NVS_H_ +#define _SOC_NVS_H_ + +#include <stdint.h> + +/* TODO - this requires xeon sp, server board support */ +/* NOTE: We do not use intelblocks/nvs.h since it includes + mostly client specific attributes */ +typedef struct global_nvs_t { + uint8_t pcnt; /* 0x00 - Processor Count */ + uint32_t cbmc; /* 0x01 - coreboot memconsole */ + uint8_t rsvd3[251]; +} __packed global_nvs_t; + +#endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pci_devs.h new file mode 100644 index 0000000..db78c82 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pci_devs.h @@ -0,0 +1,186 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PCI_DEVS_H_ +#define _SOC_PCI_DEVS_H_ + +#include <device/pci_def.h> +#include <hob_iiouds.h> + +#define dump_csr(fmt, dev, reg) \ + printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \ + fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ + ((uint32_t)dev >> 12) & 0x07, \ + #reg, reg, pci_mmio_read_config32(dev, reg)) + +#define dump_csr64(fmt, dev, reg) \ + printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \ + fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ + ((uint32_t)dev >> 12) & 0x07, #reg, reg, \ + pci_mmio_read_config32(dev, reg+4), pci_mmio_read_config32(dev, reg)) + +#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#else +#include <arch/io.h> +#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#endif + +#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define VTD_DEV 5 +#define VTD_FUNC 0 + +#define VTD_TOLM_CSR 0xd0 +#define VTD_TSEG_BASE_CSR 0xa8 +#define VTD_TSEG_LIMIT_CSR 0xac +#define VTD_EXT_CAP_LOW 0x10 +#define VTD_MMCFG_BASE_CSR 0x90 +#define VTD_MMCFG_LIMIT_CSR 0x98 +#define VTD_TOHM_CSR 0xd4 +#define VTD_MMIOL_CSR 0xdc +#define VTD_ME_BASE_CSR 0xf0 +#define VTD_ME_LIMIT_CSR 0xf8 +#define VTD_VERSION 0x00 +#define VTD_CAP 0x08 +#define VTD_CAP_LOW 0x08 +#define VTD_CAP_HIGH 0x0C +#define VTD_EXT_CAP_HIGH 0x14 + +#define SAD_ALL_DEV 29 +#define SAD_ALL_FUNC 0 +#define SAD_ALL_PAM0123_CSR 0x40 +#define SAD_ALL_PAM456_CSR 0x44 + +#define PCU_IIO_STACK 1 +#define PCU_DEV 30 +#define PCU_CR1_FUN 1 + +#define PCU_CR0_FUN 0 +#define PCU_CR0_PLATFORM_INFO 0xa8 +#define PCU_CR0_P_STATE_LIMITS 0xd8 +#define P_STATE_LIMITS_LOCK_SHIFT 31 +#define P_STATE_LIMITS_LOCK (1 << P_STATE_LIMITS_LOCK_SHIFT) +#define PCU_CR0_TEMPERATURE_TARGET 0xe4 +#define PCU_CR0_PACKAGE_RAPL_LIMIT 0xe8 +#define PCU_CR0_CURRENT_CONFIG 0xf8 +#define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ +#define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) + +#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 +#define RST_CPL1_MASK ((uint32_t)1 << 1) +#define RST_CPL2_MASK ((uint32_t)1 << 2) +#define RST_CPL3_MASK ((uint32_t)1 << 3) +#define RST_CPL4_MASK ((uint32_t)1 << 4) +#define PCODE_INIT_DONE1_MASK ((uint32_t)1 << 9) +#define PCODE_INIT_DONE2_MASK ((uint32_t)1 << 10) +#define PCODE_INIT_DONE3_MASK ((uint32_t)1 << 11) +#define PCODE_INIT_DONE4_MASK ((uint32_t)1 << 12) + +#define PCU_CR1_BIOS_MB_DATA_REG 0x8c + +#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 +#define BIOS_MB_RUN_BUSY_MASK ((uint32_t)1 << 31) +#define BIOS_MB_CMD_MASK ((uint32_t)0xff) +#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 +#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 +#define BIOS_ERR_INVALID_CMD 0x01 + +#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 +#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK ((uint32_t)1 << 31) + +#define PCU_CR1_C2C3TT_REG 0xdc +#define PCU_CR1_PCIE_ILTR_OVRD 0xfc +#define PCU_CR1_SAPMCTL 0xb0 +#define SAPMCTL_LOCK_SHIFT 31 +#define SAPMCTL_LOCK_MASK (1 << SAPMCTL_LOCK_SHIFT) +#define PCU_CR1_MC_BIOS_REQ 0x98 + +#define PCU_CR2_FUN 2 +#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK 0x8c +#define PCIE_IN_PKGCSTATE_L1_MASK 0xFFFFFF /* 23:0 bits */ +#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2 0x90 +#define KTI_IN_PKGCSTATE_L1_MASK 0x7 /* 2:0 bits */ +#define PCU_CR2_DYNAMIC_PERF_POWER_CTL 0xdc +#define UNCORE_PLIMIT_OVERRIDE_BIT 20 +#define UNOCRE_PLIMIT_OVERRIDE_SHIFT (1 << UNCORE_PLIMIT_OVERRIDE_BIT) +#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0 +#define PROCHOT_RATIO 0xa /* bits 0:7 */ + +#define UBOX_DECS_BUS 0 +#define UBOX_DECS_DEV 8 +#define UBOX_DECS_FUNC 2 +#define UBOX_DECS_CPUBUSNO_CSR 0xcc + +#define CHA_UTIL_ALL_DEV 29 +#define CHA_UTIL_ALL_FUNC 1 +#define CHA_UTIL_ALL_MMCFG_CSR 0xc0 + +#define CBDMA_DEV_NUM 0x04 +#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function +#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB + +#define VMD_DEV_NUM 5 +#define VMD_FUNC_NUM 5 + +#define APIC_DEV_NUM 5 +#define APIC_FUNC_NUM 0 + +#define PCH_IOAPIC_BUS_NUMBER 0xF0 +#define PCH_IOAPIC_DEV_NUM 0x1F +#define PCH_IOAPIC_FUNC_NUM 0x00 + +// ================================== IOAPIC Definitions for DMAR/ACPI ==================== +#define PCH_IOAPIC_ID 0x08 +#define PC00_IOAPIC_ID 0x09 +#define PC01_IOAPIC_ID 0x0A +#define PC02_IOAPIC_ID 0x0B +#define PC03_IOAPIC_ID 0x0C +#define PC04_IOAPIC_ID 0x0D +#define PC05_IOAPIC_ID 0x0E +#define PC06_IOAPIC_ID 0x0F +#define PC07_IOAPIC_ID 0x10 +#define PC08_IOAPIC_ID 0x11 +#define PC09_IOAPIC_ID 0x12 +#define PC10_IOAPIC_ID 0x13 +#define PC11_IOAPIC_ID 0x14 + +/* PCH Device info */ + +#define XHCI_BUS_NUMBER 0x0 +#define PCH_DEV_SLOT_XHCI 0x14 +#define XHCI_FUNC_NUM 0x0 + +#define HPET_BUS_NUM 0x0 +#define HPET_DEV_NUM PCH_DEV_SLOT_LPC +#define HPET0_FUNC_NUM 0x00 + +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SPI _PCH_DEV(LPC, 5) + +#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h new file mode 100644 index 0000000..c679692 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PCR_IDS_H_ +#define _PCR_IDS_H_ + +#define PID_ITSS 0xC4 +#define PID_RTC 0xC3 + +#endif /* _PCR_IDS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h new file mode 100644 index 0000000..ea111cde --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#include <soc/iomap.h> +#include <soc/pmc.h> + +#define PM1_CNT 0x04 +#define PM1_STS 0x00 +#define PM1_TMR 0x08 +#define PM2_CNT 0x50 + +#define GPE0_REG_MAX 4 +#define GPE0_STS(x) (0x80 + (x * 4)) + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h new file mode 100644 index 0000000..c080749 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PMC_H_ +#define _SOC_PMC_H_ + +/* PCI Configuration Space (D31:F2): PMC */ +#define PMC_ACPI_CNT 0x44 + +#define SCI_IRQ_SEL (7 << 0) +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 + +#define SCI_IRQ_ADJUST 0 + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h new file mode 100644 index 0000000..c012dd6 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/ramstage.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_RAMSTAGE_H_ +#define _SOC_RAMSTAGE_H_ + +#include <device/device.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memory_info.h> + +void xeon_sp_init_cpus(struct device *dev); +void mainboard_silicon_init_params(FSPS_UPD *params); + +extern struct pci_operations soc_pci_ops; + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h new file mode 100644 index 0000000..623306f --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_ROMSTAGE_H_ +#define _SOC_ROMSTAGE_H_ + +#include <fsp/api.h> + +/* These functions are weak and can be overridden by a mainboard functions. */ +void mainboard_memory_init_params(FSPM_UPD * mupd); + +#endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/soc_util.h b/src/soc/intel/xeon_sp/include/soc/soc_util.h new file mode 100644 index 0000000..8b5e1a2 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/soc_util.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_UTIL_H_ +#define _SOC_UTIL_H_ + +#include <hob_iiouds.h> +#include <hob_memmap.h> +#include <arch/acpi.h> + +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size_kb: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \ + (base_kb << 10) + (size_kb << 10) - 1, size_kb) + +#define LOG_IO_RESOURCE(type, dev, index, base, size) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \ + "end: 0x%llx, size: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) + +#define DEV_FUNC_ENTER(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ + __FILE__, __func__, __LINE__, dev_path(dev)) + +#define DEV_FUNC_EXIT(dev) \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT (dev: %s)\n", __FILE__, \ + __func__, __LINE__, dev_path(dev)) + +#define FUNC_ENTER() \ + printk(BIOS_SPEW, "%s:%s:%d: ENTER\n", __FILE__, __func__, __LINE__) + +#define FUNC_EXIT() \ + printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__) + +struct iiostack_resource { + uint8_t no_of_stacks; + STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; +}; + +uintptr_t get_tolm(uint32_t bus); +void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit); +uintptr_t get_cha_mmcfg_base(uint32_t bus); +uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory + +uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset); + +void get_stack_busnos(uint32_t *bus); +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); +void get_iiostack_info(struct iiostack_resource *info); + +int get_threads_per_package(void); +int get_platform_thread_count(void); +void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); + +unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem); +void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, + uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); + +void unlock_pam_regions(void); +void xeonsp_init_cpu_config(void); +void set_bios_init_completion(void); +void config_reset_cpl3_csrs(void); + +#endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c new file mode 100644 index 0000000..b0ba681 --- /dev/null +++ b/src/soc/intel/xeon_sp/lpc.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/ioapic.h> +#include <intelblocks/lpc_lib.h> +#include <soc/soc_util.h> +#include <soc/iomap.h> + +static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { + { 0, 0 } +}; + +const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void) +{ + return xeon_lpc_fixed_mmio_ranges; +} + +void lpc_soc_init(struct device *dev) +{ + printk(BIOS_SPEW, "pch: lpc_init\n"); + + /* FSP configures IOAPIC and PCHInterrupt Config */ + printk(BIOS_SPEW, "IOAPICID 0x%x, 0x%x\n", + io_apic_read((void *)IO_APIC_ADDR, 0x00), + ((io_apic_read((void *)IO_APIC_ADDR, 0x00) & 0x0f000000) >> 24)); +} + +void pch_lpc_soc_fill_io_resources(struct device *dev) +{ +} diff --git a/src/soc/intel/xeon_sp/reset.c b/src/soc/intel/xeon_sp/reset.c new file mode 100644 index 0000000..80a452b --- /dev/null +++ b/src/soc/intel/xeon_sp/reset.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> + +void chipset_handle_reset(uint32_t status) +{ + die("Reset not implemented!\n"); +} diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c new file mode 100644 index 0000000..dc94dc6 --- /dev/null +++ b/src/soc/intel/xeon_sp/romstage.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <intelblocks/rtc.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <soc/romstage.h> +#include <soc/soc_util.h> +#include "chip.h" + +asmlinkage void car_stage_entry(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n"); + + console_init(); + rtc_init(); + + fsp_memory_init(false); + printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n"); + + unlock_pam_regions(); + + if (postcar_frame_init(&pcf, 1 * KiB)) + die("Unable to initialize postcar frame.\n"); + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t)cbmem_top(); + printk(BIOS_DEBUG, "top_of_ram: 0x%lx\n", top_of_ram); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, + MTRR_TYPE_WRBACK); + + /* Cache the memory-mapped boot media. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + run_postcar_phase(&pcf); +} + +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) +{ +} + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + const config_t *config = config_of_soc(); + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + mupd->FspmUpdVersion = FSP_UPD_VERSION; + + // ErrorLevel - 0 (disable) to 8 (verbose) + m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; + m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; + + soc_memory_init_params(m_cfg); + + mainboard_memory_init_params(mupd); + + m_cfg->VTdConfig.VTdSupport = config->vtd_support; + m_cfg->VTdConfig.CoherencySupport = config->coherency_support; + m_cfg->VTdConfig.ATS = config->ats_support; +} diff --git a/src/soc/intel/xeon_sp/soc_util.c b/src/soc/intel/xeon_sp/soc_util.c new file mode 100644 index 0000000..6310bac --- /dev/null +++ b/src/soc/intel/xeon_sp/soc_util.c @@ -0,0 +1,577 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <commonlib/sort.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <delay.h> +#include <device/pci.h> +#include <hob_iiouds.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/pcr.h> +#include <soc/iomap.h> +#include <soc/cpu.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/soc_util.h> +#include <stdlib.h> +#include <timer.h> + +/* + * Get TOLM CSR B0:D5:F0:Offset_d0h + */ +uintptr_t get_tolm(uint32_t bus) +{ + uint32_t w = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), + VTD_TOLM_CSR); + uintptr_t addr = w & 0xfc000000; + printk(BIOS_DEBUG, "VTD_TOLM_CSR 0x%x, addr: 0x%lx\n", w, addr); + return addr; +} + +void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit) +{ + uint32_t w1 = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), + VTD_TSEG_BASE_CSR); + uint32_t wh = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC), + VTD_TSEG_LIMIT_CSR); + *base = w1 & 0xfff00000; + *limit = wh & 0xfff00000; +} + +/* + * Get MMCFG CSR B1:D29:F1:Offset_C0h + */ +uintptr_t get_cha_mmcfg_base(uint32_t bus) +{ + uint32_t wl = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, + CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR); + uint32_t wh = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV, + CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR + 4); + uintptr_t addr = ((((wh & 0x3fff) << 6) | ((wl >> 26) & 0x3f)) << 26); + printk(BIOS_DEBUG, "CHA_UTIL_ALL_MMCFG_CSR wl: 0x%x, wh: 0x%x, addr: 0x%lx\n", + wl, wh, addr); + return addr; +} + +/* + * Get Socket 0 CPUBUSNO(0), CPUBUSNO(1) PCI bus numbers UBOX (B0:D8:F2:Offset_CCh) + * TODO: D0h + */ +void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3) +{ + uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, + UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR); + if (bus0) + *bus0 = (bus & 0xff); + if (bus1) + *bus1 = (bus >> 8) & 0xff; + if (bus2) + *bus2 = (bus >> 16) & 0xff; + if (bus3) + *bus3 = (bus >> 24) & 0xff; +} + +uint32_t top_of_32bit_ram(void) +{ + uintptr_t mmcfg, tolm; + uint32_t bus0 = 0, bus1 = 0; + uint32_t base = 0, limit = 0; + + get_cpubusnos(&bus0, &bus1, NULL, NULL); + + mmcfg = get_cha_mmcfg_base(bus1); + tolm = get_tolm(bus0); + printk(BIOS_DEBUG, "bus0: 0x%x, bus1: 0x%x, mmcfg: 0x%lx, tolm: 0x%lx\n", + bus0, bus1, mmcfg, tolm); + get_tseg_base_lim(bus0, &base, &limit); + printk(BIOS_DEBUG, "tseg base: 0x%x, limit: 0x%x\n", base, limit); + + /* We will use TSEG base as the top of DRAM */ + return base; +} + +/* + * +-------------------------+ TOLM + * | System Management Mode | + * | code and data | + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + +uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset) +{ + return pci_mmio_read_config32(PCI_DEV(bus, dev, func), offset); +} + +uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +{ + size_t hob_size; + const IIO_UDS *hob; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + + assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); + + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; +} + +/* bus needs to be of size 6 (MAX_IIO_STACK) */ +void get_stack_busnos(uint32_t *bus) +{ + uint32_t reg1, reg2; + + reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xcc); + reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC), + 0xd0); + + for (int i = 0; i < 4; ++i) + bus[i] = ((reg1 >> (i * 8)) & 0xff); + for (int i = 0; i < 2; ++i) + bus[4+i] = ((reg2 >> (i * 8)) & 0xff); +} + +void unlock_pam_regions(void) +{ + uint32_t bus1 = 0; + uint32_t pam0123_unlock_dram = 0x33333330; + uint32_t pam456_unlock_dram = 0x00333333; + + get_cpubusnos(NULL, &bus1, NULL, NULL); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM456_CSR, pam456_unlock_dram); + + uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); + uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); + printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", + __FILE__, __func__, reg1, reg2); +} + +/* return 1 if command timed out else 0 */ +static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask, + uint32_t target) +{ + uint32_t max_delay = 5000; /* 5 seconds max */ + uint32_t step_delay = 50; /* 50 us */ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, max_delay); + while ((pci_mmio_read_config32(dev, reg) & mask) != target) { + udelay(step_delay); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "%s timed out for dev: 0x%x, reg: 0x%x, " + "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target); + return 1; /* timedout */ + } + } + return 0; /* successful */ +} + +/* return 1 if command timed out else 0 */ +static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, + uint32_t pcode_init_mask, uint32_t val) +{ + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); + reg &= (uint32_t) ~rst_cpl_mask; + reg |= rst_cpl_mask; + reg |= val; + + /* update BIOS RESET completion bit */ + pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); + + /* wait for PCU ack */ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, + pcode_init_mask); +} + +/* return 1 if command timed out else 0 */ +static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) +{ + /* verify bios is not in busy state */ + if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0)) + return 1; /* timed out */ + + /* write data to data register */ + printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__, + PCU_CR1_BIOS_MB_DATA_REG, data); + pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data); + + /* write the command */ + printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__, + PCU_CR1_BIOS_MB_INTERFACE_REG, + (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK)); + pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, + (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK)); + + /* wait for completion or time out*/ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, + BIOS_MB_RUN_BUSY_MASK, 0); +} + +void config_reset_cpl3_csrs(void) +{ + uint32_t data, plat_info, max_min_turbo_limit_ratio; + + for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + + /* configure PCU_CR0_FUN csrs */ + pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); + data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); + data |= P_STATE_LIMITS_LOCK; + pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); + + plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); + dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); + max_min_turbo_limit_ratio = + (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> + MAX_NON_TURBO_LIM_RATIO_SHIFT; + printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", + plat_info, max_min_turbo_limit_ratio); + + /* configure PCU_CR1_FUN csrs */ + pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL); + /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ + data &= 0x0fffffff; + data |= SAPMCTL_LOCK_MASK; + pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); + + /* configure PCU_CR1_FUN csrs */ + pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); + + data = PCIE_IN_PKGCSTATE_L1_MASK; + pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); + + data = KTI_IN_PKGCSTATE_L1_MASK; + pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); + + data = PROCHOT_RATIO; + printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); + pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); + dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); + + data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); + data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; + pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); + } +} + +static void set_bios_init_completion_for_package(uint32_t socket) +{ + uint32_t data; + uint32_t timedout; + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + /* read pcu config */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) { + /* 2nd try */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); + if (timedout) + die("BIOS PCU Misc Config Read timed out.\n"); + + data = pci_mmio_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG); + printk(BIOS_SPEW, "%s - pci_mmio_read_config32 reg: 0x%x, data: 0x%x\n", + __func__, PCU_CR1_BIOS_MB_DATA_REG, data); + + /* write PCU config */ + timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data); + if (timedout) + die("BIOS PCU Misc Config Write timed out.\n"); + } + + /* update RST_CPL3, PCODE_INIT_DONE3 */ + timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK, + PCODE_INIT_DONE3_MASK, RST_CPL3_MASK); + if (timedout) + die("BIOS RESET CPL3 timed out.\n"); + + /* update RST_CPL4, PCODE_INIT_DONE4 */ + timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, + PCODE_INIT_DONE4_MASK, RST_CPL4_MASK); + if (timedout) + die("BIOS RESET CPL4 timed out.\n"); + /* set CSR_DESIRED_CORES_CFG2 lock bit */ + data = pci_mmio_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG); + data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK; + printk(BIOS_SPEW, "%s - pci_mmio_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n", + __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data); + pci_mmio_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data); +} + +void set_bios_init_completion(void) +{ + uint32_t sbsp_socket_id = 0; /* TODO - this needs to be configurable */ + + for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { + if (socket == sbsp_socket_id) + continue; + set_bios_init_completion_for_package(socket); + } + set_bios_init_completion_for_package(sbsp_socket_id); +} + +void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) +{ + register int ecx; + struct cpuid_result cpuid_regs; + + /* get max index of CPUID */ + cpuid_regs = cpuid(0); + assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ + + *thread_bits = *core_bits = 0; + ecx = 0; + while (1) { + cpuid_regs = cpuid_ext(0xb, ecx); + if (ecx == 0) { + *thread_bits = (cpuid_regs.eax & 0x1f); + } else { + *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; + break; + } + ecx++; + } +} + +void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, + uint8_t *package, uint8_t *core, uint8_t *thread) +{ + if (package != NULL) + *package = (apicid >> (thread_bits + core_bits)); + if (core != NULL) + *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); + if (thread != NULL) + *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); +} + +int get_cpu_count(void) +{ + size_t hob_size; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; + + /* these fields are incorrect - need debugging */ + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + return hob->SystemStatus.numCpus; +} + +int get_threads_per_package(void) +{ + unsigned int core_count, thread_count; + cpu_read_topology(&core_count, &thread_count); + return thread_count; +} + +int get_platform_thread_count(void) +{ + return get_cpu_count() * get_threads_per_package(); +} + +void get_iiostack_info(struct iiostack_resource *info) +{ + size_t hob_size; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; + + hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + // copy IIO Stack info from FSP HOB + info->no_of_stacks = 0; + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + for (int x = 0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + // TODO: do we have situation with only bux 0 and one stack? + if (ri->BusBase >= ri->BusLimit) + continue; + assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); + memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); + } + } +} + +#if ENV_RAMSTAGE + +void xeonsp_init_cpu_config(void) +{ + struct device *dev; + int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; + int num_apics = 0; + uint32_t core_bits, thread_bits; + unsigned int core_count, thread_count; + unsigned int num_cpus; + + /* sort APIC ids in asending order to identify apicid ranges for + each numa domain + */ + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + apic_ids[num_apics++] = dev->path.apic.apic_id; + } + if (num_apics > 1) + bubblesort(apic_ids, num_apics, NUM_ASCENDING); + + num_cpus = get_cpu_count(); + cpu_read_topology(&core_count, &thread_count); + assert(num_apics == (num_cpus * thread_count)); + + /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ + int index = 0; + for (int id = 0; id < num_apics; ++id) { + int apic_id = apic_ids[id]; + if (apic_id & 0x1) { /* 2nd thread */ + apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; + } else { /* 1st thread */ + apic_ids_by_thread[index++] = apic_id; + } + } + + + /* update apic_id, node_id in sorted order */ + num_apics = 0; + get_core_thread_bits(&core_bits, &thread_bits); + for (dev = all_devices; dev; dev = dev->next) { + uint8_t package; + + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; + get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, + &package, NULL, NULL); + dev->path.apic.node_id = package; + printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", + num_apics, dev->path.apic.apic_id, + dev->path.apic.apic_id, dev->path.apic.node_id); + + ++num_apics; + } +} + +unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) +{ + const struct SystemMemoryMapHob *memory_map; + size_t hob_size; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + unsigned int mmap_index; + + memory_map = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + assert(memory_map != NULL && hob_size != 0); + printk(BIOS_DEBUG, "FSP_SYSTEM_MEMORYMAP_HOB_GUID hob_size: %ld\n", hob_size); + + mmap_index = 0; + for (int e = 0; e < memory_map->numberEntries; ++e) { + const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e]; + uint64_t addr = + (uint64_t) ((uint64_t)mem_element->BaseAddress << + MEM_ADDR_64MB_SHIFT_BITS); + uint64_t size = + (uint64_t) ((uint64_t)mem_element->ElementSize << + MEM_ADDR_64MB_SHIFT_BITS); + + printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, " + "ElementSize: 0x%x, reserved: %d\n", + e, addr, mem_element->BaseAddress, size, + mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED)); + + assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT); + + /* skip reserved memory region */ + if (mem_element->Type & MEM_TYPE_RESERVED) + continue; + + /* skip if this address is already added */ + bool skip = false; + for (int idx = 0; idx < mmap_index; ++idx) { + uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) + + srat_mem[idx].base_address_low; + if (addr == base_addr) { + skip = true; + break; + } + } + if (skip) + continue; + + srat_mem[mmap_index].type = 1; /* Memory affinity structure */ + srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t); + srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff); + srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32); + srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff); + srat_mem[mmap_index].length_high = (uint32_t) (size >> 32); + srat_mem[mmap_index].proximity_domain = mem_element->SocketId; + srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; + if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) + srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; + ++mmap_index; + } + + return mmap_index; +} + +#endif diff --git a/src/soc/intel/xeon_sp/spi.c b/src/soc/intel/xeon_sp/spi.c new file mode 100644 index 0000000..18af5e4 --- /dev/null +++ b/src/soc/intel/xeon_sp/spi.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/spi.h> +#include <soc/pci_devs.h> + +int spi_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_SPI: + return 0; + } + return -1; +} diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c new file mode 100644 index 0000000..adf3e3e --- /dev/null +++ b/src/soc/intel/xeon_sp/uncore.c @@ -0,0 +1,305 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <soc/soc_util.h> + +struct map_entry { + uint32_t reg; + int is_64_bit; + int is_limit; + int mask_bits; + const char *description; +}; + +enum { + TOHM_REG, + MMIOL_REG, + MMCFG_BASE_REG, + MMCFG_LIMIT_REG, + TOLM_REG, + ME_BASE_REG, + ME_LIMIT_REG, + TSEG_BASE_REG, + TSEG_LIMIT_REG, + /* Must be last. */ + NUM_MAP_ENTRIES +}; + +static struct map_entry memory_map[NUM_MAP_ENTRIES] = { + [TOHM_REG] = MAP_ENTRY_LIMIT_64(VTD_TOHM_CSR, 26, "TOHM"), + [MMIOL_REG] = MAP_ENTRY_BASE_32(VTD_MMIOL_CSR, "MMIOL"), + [MMCFG_BASE_REG] = MAP_ENTRY_BASE_64(VTD_MMCFG_BASE_CSR, "MMCFG_BASE"), + [MMCFG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_MMCFG_LIMIT_CSR, 26, "MMCFG_LIMIT"), + [TOLM_REG] = MAP_ENTRY_LIMIT_32(VTD_TOLM_CSR, 26, "TOLM"), + [ME_BASE_REG] = MAP_ENTRY_BASE_64(VTD_ME_BASE_CSR, "ME_BASE"), + [ME_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_ME_LIMIT_CSR, 19, "ME_LIMIT"), + [TSEG_BASE_REG] = MAP_ENTRY_BASE_32(VTD_TSEG_BASE_CSR, "TSEGMB_BASE"), + [TSEG_LIMIT_REG] = MAP_ENTRY_LIMIT_32(VTD_TSEG_LIMIT_CSR, 20, "TSEGMB_LIMIT"), +}; + +static void read_map_entry(struct device *dev, struct map_entry *entry, + uint64_t *result) +{ + uint64_t value; + uint64_t mask; + + /* All registers are on a 1MiB granularity. */ + mask = ((1ULL << entry->mask_bits) - 1); + mask = ~mask; + + value = 0; + + if (entry->is_64_bit) { + value = pci_read_config32(dev, entry->reg + sizeof(uint32_t)); + value <<= 32; + } + + value |= (uint64_t)pci_read_config32(dev, entry->reg); + value &= mask; + + if (entry->is_limit) + value |= ~mask; + + *result = value; +} + +static void mc_read_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) + read_map_entry(dev, &memory_map[i], &values[i]); +} + +static void mc_report_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", + memory_map[i].description, values[i]); + } +} + +/* + * Host Memory Map: + * + * +--------------------------+ TOCM (2 pow 46 - 1) + * | Reserved | + * +--------------------------+ + * | MMIOH (relocatable) | + * +--------------------------+ + * | PCISeg | + * +--------------------------+ TOHM + * | High DRAM Memory | + * +--------------------------+ 4GiB (0x100000000) + * +--------------------------+ 0xFFFF_FFFF + * | Firmware | + * +--------------------------+ 0xFF00_0000 + * | Reserved | + * +--------------------------+ 0xFEF0_0000 + * | Local xAPIC | + * +--------------------------+ 0xFEE0_0000 + * | HPET/LT/TPM/Others | + * +--------------------------+ 0xFED0_0000 + * | I/O xAPIC | + * +--------------------------+ 0xFEC0_0000 + * | Reserved | + * +--------------------------+ 0xFEB8_0000 + * | Reserved | + * +--------------------------+ 0xFEB0_0000 + * | Reserved | + * +--------------------------+ 0xFE00_0000 + * | MMIOL (relocatable) | + * | P2SB PCR cfg BAR | (0xfd000000 - 0xfdffffff + * | BAR space | [mem 0x90000000-0xfcffffff] available for PCI devices + * +--------------------------+ 0x9000_0000 + * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB + * | | (0x80000000 - 0x8fffffff, 0x40000) + * +--------------------------+ TOLM + * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) + * +--------------------------+ + * | Tseg (relocatable) | N x 8MB (0x70000000 - 0x77ffffff, 0x20000) + * +--------------------------+ cbmem_top + * | Reserved - CBMEM | (0x6fffe000 - 0x6fffffff, 0x2000) + * +--------------------------+ + * | Reserved - FSP | (0x6fbfe000 - 0x6fffdfff, 0x400000) + * +--------------------------+ top_of_ram (0x6fbfdfff) + * | Low DRAM Memory | + * +--------------------------+ FFFFF (1MB) + * | E & F segments | + * +--------------------------+ E0000 + * | C & D segments | + * +--------------------------+ C0000 + * | VGA & SMM Memory | + * +--------------------------+ A0000 + * | Conventional Memory | + * | (DOS Range) | + * +--------------------------+ 0 + */ + +static void mc_add_dram_resources(struct device *dev, int *res_count) +{ + struct range_entry fsp_mem; + uint64_t base_kb; + uint64_t size_kb; + uint64_t top_of_ram; + uint64_t mc_values[NUM_MAP_ENTRIES]; + struct resource *resource; + int index = *res_count; + + fsp_find_reserved_memory(&fsp_mem); + + /* Read in the MAP registers and report their values. */ + mc_read_map_entries(dev, &mc_values[0]); + mc_report_map_entries(dev, &mc_values[0]); + + top_of_ram = range_entry_base(&fsp_mem) - 1; + printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", + (uintptr_t) cbmem_top(), range_entry_base(&fsp_mem), + range_entry_end(&fsp_mem), top_of_ram); + + /* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */ + base_kb = 0; + size_kb = (0xa0000 >> 10); + LOG_MEM_RESOURCE("legacy_ram", dev, index, base_kb, size_kb); + ram_resource(dev, index++, base_kb, size_kb); + + /* 1MB -> top_of_ram i.e., fsp_mem_base+1*/ + base_kb = (0x100000 >> 10); + size_kb = (top_of_ram - 0xfffff) >> 10; + LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb); + ram_resource(dev, index++, base_kb, size_kb); + + /* + * FSP meomoy, CBMem regions are already added as reserved + * Add TSEG and MESEG Regions as reserved memory + * src/drivers/intel/fsp2_0/memory_init.c sets CBMEM reserved size + * arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); == 2 * CBMEM_ROOT_MIN_SIZE + * typically 0x2000 + * Example config: + * FSP_RESERVED_MEMORY_RESOURCE_HOB + * FspReservedMemoryResource Base : 6FBFE000 + * FspReservedMemoryResource Size : 400000 + * FSP_BOOT_LOADER_TOLUM_HOB + * FspBootLoaderTolum Base : 6FFFE000 + * FspBootLoaderTolum Size : 2000 + */ + + /* Mark TSEG/SMM region as reserved */ + base_kb = (mc_values[TSEG_BASE_REG] >> 10); + size_kb = (mc_values[TSEG_LIMIT_REG] - mc_values[TSEG_BASE_REG] + 1) >> 10; + LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb); + reserved_ram_resource(dev, index++, base_kb, size_kb); + + /* Mark region between TSEG - TOLM (eg. MESEG) as reserved */ + if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) { + base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10); + size_kb = (mc_values[TOLM_REG] - mc_values[TSEG_LIMIT_REG]) >> 10; + LOG_MEM_RESOURCE("mmio_tolm", dev, index, base_kb, size_kb); + reserved_ram_resource(dev, index++, base_kb, size_kb); + } + + /* 4GiB -> TOHM */ + if (mc_values[TOHM_REG] > 0x100000000) { + base_kb = (0x100000000 >> 10); + size_kb = (mc_values[TOHM_REG] - 0x100000000 + 1) >> 10; + LOG_MEM_RESOURCE("high_ram", dev, index, base_kb, size_kb); + ram_resource(dev, index++, base_kb, size_kb); + } + + /* add MMIO CFG resource */ + resource = new_resource(dev, index++); + resource->base = (resource_t) mc_values[MMCFG_BASE_REG]; + resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - + mc_values[MMCFG_BASE_REG] + 1); + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), + (resource->size >> 10)); + + /* add Local APIC resource */ + resource = new_resource(dev, index++); + resource->base = LAPIC_DEFAULT_BASE; + resource->size = 0x00001000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), + (resource->size >> 10)); + + /* + * Add legacy region as reserved - 0xa000 - 1MB + * Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + base_kb = VGA_BASE_ADDRESS >> 10; + size_kb = VGA_BASE_SIZE >> 10; + LOG_MEM_RESOURCE("legacy_mmio", dev, index, base_kb, size_kb); + mmio_resource(dev, index++, base_kb, size_kb); + + base_kb = (0xc0000 >> 10); + size_kb = (0x100000 - 0xc0000) >> 10; + LOG_MEM_RESOURCE("legacy_write_protect", dev, index, base_kb, size_kb); + reserved_ram_resource(dev, index++, base_kb, size_kb); + + *res_count = index; +} + +static void mmapvtd_read_resources(struct device *dev) +{ + int index = 0; + + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev, &index); +} + +static void mmapvtd_init(struct device *dev) +{ +} + +static struct device_operations mmapvtd_ops = { + .read_resources = mmapvtd_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = mmapvtd_init, + .ops_pci = &soc_pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_inject_dsdt_generator = NULL, +#endif +}; + +static const unsigned short mmapvtd_ids[] = { + MMAP_VTD_CFG_REG_DEVID, /* Memory Map/Intel® VT-d Configuration Registers */ + 0 +}; + +static const struct pci_driver mmapvtd_driver __pci_driver = { + .ops = &mmapvtd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = mmapvtd_ids +}; diff --git a/src/soc/intel/xeon_sp/upd_display.c b/src/soc/intel/xeon_sp/upd_display.c new file mode 100644 index 0000000..2ae34ed --- /dev/null +++ b/src/soc/intel/xeon_sp/upd_display.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 - 2020 Intel Corporation + * Copyright (C) 2019 - 2020 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> + +#define DUMP_UPD(old, new, field) \ + fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field) + +/* Display the UPD parameters for MemoryInit */ +void soc_display_fspm_upd_params( + const FSPM_UPD *fspm_old_upd, + const FSPM_UPD *fspm_new_upd) +{ + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old; + + old = &fspm_old_upd->FspmConfig; + new = &fspm_new_upd->FspmConfig; + + printk(BIOS_DEBUG, "UPD values for MemoryInit:\n"); + + DUMP_UPD(old, new, PcdFspMrcDebugPrintErrorLevel); + DUMP_UPD(old, new, PcdFspKtiDebugPrintErrorLevel); + DUMP_UPD(old, new, PcdHsuartDevice); + + hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); +} + +/* Display the UPD parameters for SiliconInit */ +void soc_display_fsps_upd_params( + const FSPS_UPD *fsps_old_upd, + const FSPS_UPD *fsps_new_upd) +{ + const FSPS_CONFIG *new; + const FSPS_CONFIG *old; + + old = &fsps_old_upd->FspsConfig; + new = &fsps_new_upd->FspsConfig; + + printk(BIOS_DEBUG, "UPD values for SiliconInit:\n"); + + DUMP_UPD(old, new, PcdBifurcationPcie0); + DUMP_UPD(old, new, PcdBifurcationPcie1); + DUMP_UPD(old, new, PcdActiveCoreCount); + DUMP_UPD(old, new, PcdCpuMicrocodePatchBase); + DUMP_UPD(old, new, PcdCpuMicrocodePatchSize); + DUMP_UPD(old, new, PcdEnablePcie0); + DUMP_UPD(old, new, PcdEnablePcie1); + DUMP_UPD(old, new, PcdEnableEmmc); + DUMP_UPD(old, new, PcdEnableGbE); + DUMP_UPD(old, new, PcdFiaMuxConfigRequestPtr); + DUMP_UPD(old, new, PcdPcieRootPort0DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort1DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort2DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort3DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort4DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort5DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort6DeEmphasis); + DUMP_UPD(old, new, PcdPcieRootPort7DeEmphasis); + DUMP_UPD(old, new, PcdEMMCDLLConfigPtr); + + hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); +}
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 54:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1141 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1140 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1139
Please note: This test is under development and might not be accurate at all!
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 54:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/chip... PS54, Line 269: static void assign_bridge_resources(struct iiostack_resource *stack_list, Could someone please provide commentary on what all this resource manipulation is doing in the chipset code? There's a lot of it, and it doesn't seem appropriate. Similarly, there's not much of anything in this file explaining what is going on and why.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 54:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/chip... PS54, Line 269: static void assign_bridge_resources(struct iiostack_resource *stack_list,
Could someone please provide commentary on what all this resource manipulation is doing in the chips […]
Hi Aaron, in Xeon Scalable Processor, there is a concept of (Integrated IO) stack. Each stack can be considered to be a root port, it needs to be assigned with IO/memory resource that is big enough and aligned to meet the needs of all PCIe devices in the stack. This is similar to resource reservation for PCIe bridge device in consideration of PCIe end point devices, but it is one another hierarchy. If any further clarification/discussion is needed, let's chat (through either messenger such as slack or phone call, or both).
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 54:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/chip... File src/soc/intel/xeon_sp/chip.c:
https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/chip... PS54, Line 269: static void assign_bridge_resources(struct iiostack_resource *stack_list,
Hi Aaron, in Xeon Scalable Processor, there is a concept of (Integrated IO) stack. Each stack can be considered to be a root port, it needs to be assigned with IO/memory resource that is big enough and aligned to meet the needs of all PCIe devices in the stack. This is similar to resource reservation for PCIe bridge device in consideration of PCIe end point devices, but it is one another hierarchy. If any further clarification/discussion is needed, let's chat (through either messenger such as slack or phone call, or both).
Then we should model that more appropriately instead of open coding this approach. Do you think you could write up more concretely the requirements so we can come up with an approach that more accurately fits into coreboot? I feel like we're sidestepping some core coreboot implementation details by taking this approach.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: soc/intel: Add Intel Xeon Scalable Processor support ......................................................................
Patch Set 54:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/Kcon... File src/soc/intel/xeon_sp/Kconfig:
https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/Kcon... PS54, Line 60: config MAINBOARD_USES_FSP2_0 Hmmm, I don't understand this... what else would a board use? and why does this option exist if there is no board that disables it and the Makefiles assume that it is always set?
Also, why is it declared here and then in the subdirectories again?
-
9elements QA (Code Review) -
Aaron Durbin (Code Review)
-
Andrey Petrov (Code Review)
-
Angel Pons (Code Review)
-
Anjaneya "Reddy" Chagam (Code Review)
-
build bot (Jenkins) (Code Review)
-
David Hendricks (Code Review)
-
HAOUAS Elyes (Code Review)
-
Johnny Lin (Code Review)
-
Jonathan Zhang (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)