HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39373 )
Change subject: src/sb: Use 'print("%s...", __func__)' ......................................................................
src/sb: Use 'print("%s...", __func__)'
Change-Id: Ie0d845d3e501ed5ebeef1997944445d31768e410 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/cimx/sb800/smbus.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 39 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39373/1
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index d586d33..7cd8e15 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -52,7 +52,7 @@
void hudson_enable(struct device *dev) { - printk(BIOS_DEBUG, "hudson_enable()\n"); + printk(BIOS_DEBUG, "%s()\n", __func__); switch (dev->path.pci.devfn) { case PCI_DEVFN(0x14, 5): if (dev->enabled == 0) { diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 7f76cd5..c53faf1 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -26,7 +26,7 @@
void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { - printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); + printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); }
/** Set the EOS bit and enable SMI generation from southbridge */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 21c578f..0882100 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -122,7 +122,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
cmos_check_update_date();
@@ -136,7 +136,7 @@ setup_i8259(); /* Initialize i8259 pic */ setup_i8254(); /* Initialize i8254 timers */
- printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); + printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); }
unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 79f4029..f296870 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -25,7 +25,7 @@ { struct resource *res;
- printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
@@ -51,14 +51,14 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
compact_resources(dev); - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); }
void lpc_set_resources(struct device *dev) { struct resource *res;
- printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__);
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ res = find_resource(dev, 2); @@ -66,7 +66,7 @@
pci_dev_set_resources(dev);
- printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); }
/** @@ -82,7 +82,7 @@ int var_num = 0; u16 reg_var[3];
- printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48);
@@ -180,5 +180,5 @@ //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - End.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); } diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index a4426ff..ba2a099 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -63,11 +63,11 @@ u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the device I'm talking to */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
@@ -84,7 +84,7 @@ /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTCMD);
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return byte; }
@@ -93,11 +93,11 @@ u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the command... */ outb(val, smbus_io_base + SMBHSTCMD);
@@ -114,7 +114,7 @@ return -3; /* timeout or error */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return 0; }
@@ -123,11 +123,11 @@ u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
@@ -147,7 +147,7 @@ /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTDAT0);
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return byte; }
@@ -156,11 +156,11 @@ u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
@@ -180,7 +180,7 @@ return -3; /* timeout or error */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return 0; }
@@ -188,7 +188,7 @@ { u32 tmp;
- printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -204,14 +204,14 @@ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); }
void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) { u32 tmp;
- printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -227,7 +227,7 @@ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); }
/* space = 0: AX_INDXC, AX_DATAC @@ -237,7 +237,7 @@ { u32 tmp;
- printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* read axindc to tmp */ outl(space << 29 | space << 3 | 0x30, AB_INDX); outl(axindc, AB_DATA); @@ -256,5 +256,5 @@ outl(space << 29 | space << 3 | 0x34, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); } diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 51c37a1..831b7f8 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -39,7 +39,7 @@
void hudson_enable(struct device *dev) { - printk(BIOS_DEBUG, "hudson_enable()\n"); + printk(BIOS_DEBUG, "%s()\n", __func__); switch (dev->path.pci.devfn) { case PCI_DEVFN(0x14, 7): /* SD */ if (dev->enabled == 0) { diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 7f76cd5..c53faf1 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -26,7 +26,7 @@
void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { - printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); + printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); }
/** Set the EOS bit and enable SMI generation from southbridge */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 01576a6..da135fa 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -455,7 +455,7 @@ { const config_t *const config = dev->chip_info;
- printk(BIOS_DEBUG, "pch_spi_init\n"); + printk(BIOS_DEBUG, "%s\n", __func__);
if (config->spi_uvscc) RCBA32(0x3800 + 0xc8) = config->spi_uvscc; @@ -535,7 +535,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Print detected platform */ report_pch_info(dev); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 779d319..dd672a2 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -372,7 +372,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801gx: lpc_init\n"); + printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index bac48c2..5cf9e08 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -382,7 +382,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801ix: lpc_init\n"); + printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 91b1bde..05c47cc 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -387,7 +387,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801jx: lpc_init\n"); + printk(BIOS_DEBUG, "i82801jx: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 4fbf329..2178e99 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -83,13 +83,13 @@ *pWindowRegister = (*pWindowRegister & ~(0x0f << 24)) | apic_id; // Set the ID
if ((*pWindowRegister & (0x0f << 24)) != apic_id) - die("p64h2_ioapic_init failed"); + die("%s failed", __func__);
*pIndexRegister = 3; // Select Boot Configuration register *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts
if (!(*pWindowRegister & 1)) - die("p64h2_ioapic_init failed"); + die("%s failed", __func__); }
static struct device_operations ioapic_ops = { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 851f4f5..636ec82 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -457,7 +457,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4b39829..e5d49b9 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -525,7 +525,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f);
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39373 )
Change subject: src/sb: Use 'print("%s...", __func__)' ......................................................................
Patch Set 1:
(18 comments)
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/smbus.c:
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 65: if (smbus_wait_until_ready(smbus_io_base) < 0) { suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 70: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 87: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 95: if (smbus_wait_until_ready(smbus_io_base) < 0) { suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 100: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 117: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 125: if (smbus_wait_until_ready(smbus_io_base) < 0) { suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 130: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 150: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 158: if (smbus_wait_until_ready(smbus_io_base) < 0) { suspect code indent for conditional statements (8, 8)
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 163: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 183: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 191: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 207: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 214: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 230: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 240: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/39373/1/src/southbridge/amd/cimx/sb... PS1, Line 259: printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); please, no spaces at the start of a line
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39373
to look at the new patch set (#2).
Change subject: src/sb: Use 'print("%s...", __func__)' ......................................................................
src/sb: Use 'print("%s...", __func__)'
Change-Id: Ie0d845d3e501ed5ebeef1997944445d31768e410 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/cimx/sb800/smbus.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 39 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39373/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39373 )
Change subject: src/sb: Use 'print("%s...", __func__)' ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39373/2/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/smbus.c:
https://review.coreboot.org/c/coreboot/+/39373/2/src/southbridge/amd/cimx/sb... PS2, Line 95: if (smbus_wait_until_ready(smbus_io_base) < 0) { suspect code indent for conditional statements (8, 8)
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39373
to look at the new patch set (#3).
Change subject: src/sb: Use 'print("%s...", __func__)' ......................................................................
src/sb: Use 'print("%s...", __func__)'
Change-Id: Ie0d845d3e501ed5ebeef1997944445d31768e410 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/cimx/sb800/smbus.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 39 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/39373/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39373 )
Change subject: src/sb: Use 'print("%s...", __func__)' ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39373 )
Change subject: src/sb: Use 'print("%s...", __func__)' ......................................................................
src/sb: Use 'print("%s...", __func__)'
Change-Id: Ie0d845d3e501ed5ebeef1997944445d31768e410 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/39373 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/cimx/sb800/smbus.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 39 insertions(+), 39 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 3f04987..3609314 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -39,7 +39,7 @@
void hudson_enable(struct device *dev) { - printk(BIOS_DEBUG, "hudson_enable()\n"); + printk(BIOS_DEBUG, "%s()\n", __func__); switch (dev->path.pci.devfn) { case PCI_DEVFN(0x14, 5): if (dev->enabled == 0) { diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 567a3f8..9e6db34 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -12,7 +12,7 @@
void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { - printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); + printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); }
/** Set the EOS bit and enable SMI generation from southbridge */ diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index cf84b21..1cf3ae8 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -108,7 +108,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__);
cmos_check_update_date();
@@ -122,7 +122,7 @@ setup_i8259(); /* Initialize i8259 pic */ setup_i8254(); /* Initialize i8254 timers */
- printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); + printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); }
unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 9517d95..a082e0c 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -11,7 +11,7 @@ { struct resource *res;
- printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
@@ -37,14 +37,14 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
compact_resources(dev); - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); }
void lpc_set_resources(struct device *dev) { struct resource *res;
- printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__);
/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ res = find_resource(dev, 2); @@ -52,7 +52,7 @@
pci_dev_set_resources(dev);
- printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); }
/** @@ -68,7 +68,7 @@ int var_num = 0; u16 reg_var[3];
- printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48);
@@ -166,5 +166,5 @@ //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } - printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - End.\n"); + printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); } diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index bc9d921..86bde26 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -50,11 +50,11 @@ u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the device I'm talking to */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
@@ -71,7 +71,7 @@ /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTCMD);
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return byte; }
@@ -80,11 +80,11 @@ u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the command... */ outb(val, smbus_io_base + SMBHSTCMD);
@@ -101,7 +101,7 @@ return -3; /* timeout or error */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return 0; }
@@ -110,11 +110,11 @@ u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
@@ -134,7 +134,7 @@ /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTDAT0);
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return byte; }
@@ -143,11 +143,11 @@ u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - smbus not ready.\n", __func__); return -2; /* not ready */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
@@ -167,7 +167,7 @@ return -3; /* timeout or error */ }
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); return 0; }
@@ -175,7 +175,7 @@ { u32 tmp;
- printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -191,14 +191,14 @@ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); }
void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) { u32 tmp;
- printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -214,7 +214,7 @@ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); }
/* space = 0: AX_INDXC, AX_DATAC @@ -224,7 +224,7 @@ { u32 tmp;
- printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - Start.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - Start.\n", __func__); /* read axindc to tmp */ outl(space << 29 | space << 3 | 0x30, AB_INDX); outl(axindc, AB_DATA); @@ -243,5 +243,5 @@ outl(space << 29 | space << 3 | 0x34, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - End.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - %s - End.\n", __func__); } diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 63fe473..852144b 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -26,7 +26,7 @@
void hudson_enable(struct device *dev) { - printk(BIOS_DEBUG, "hudson_enable()\n"); + printk(BIOS_DEBUG, "%s()\n", __func__); switch (dev->path.pci.devfn) { case PCI_DEVFN(0x14, 7): /* SD */ if (dev->enabled == 0) { diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 567a3f8..9e6db34 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -12,7 +12,7 @@
void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { - printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); + printk(BIOS_DEBUG, "%s STUB!!!\n", __func__); }
/** Set the EOS bit and enable SMI generation from southbridge */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0341de2..987db36 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -446,7 +446,7 @@ { const config_t *const config = dev->chip_info;
- printk(BIOS_DEBUG, "pch_spi_init\n"); + printk(BIOS_DEBUG, "%s\n", __func__);
if (config->spi_uvscc) RCBA32(0x3800 + 0xc8) = config->spi_uvscc; @@ -526,7 +526,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Print detected platform */ report_pch_info(dev); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index b69dba4..7e2b5a7 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -354,7 +354,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801gx: lpc_init\n"); + printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 455e3b8..37f9852 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -366,7 +366,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801ix: lpc_init\n"); + printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 73eaede..ae98fdd 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -371,7 +371,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801jx: lpc_init\n"); + printk(BIOS_DEBUG, "i82801jx: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 6be212f..4763703 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -72,13 +72,13 @@ *pWindowRegister = (*pWindowRegister & ~(0x0f << 24)) | apic_id; // Set the ID
if ((*pWindowRegister & (0x0f << 24)) != apic_id) - die("p64h2_ioapic_init failed"); + die("%s failed", __func__);
*pIndexRegister = 3; // Select Boot Configuration register *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts
if (!(*pWindowRegister & 1)) - die("p64h2_ioapic_init failed"); + die("%s failed", __func__); }
static struct device_operations ioapic_ops = { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f1fa0d2..0d15b5d 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -441,7 +441,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 3535312..7e1355a 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -509,7 +509,7 @@
static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "pch: lpc_init\n"); + printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f);
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39373 )
Change subject: src/sb: Use 'print("%s...", __func__)' ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4023 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4022 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4021 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4020
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
build bot (Jenkins) (Code Review)
-
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)