Change in coreboot[master]: soc/broadwell: Allow disabling of PCIe ASPM options

[Youness Alaoui (Code Review)]

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19899 )

Change subject: soc/broadwell: Allow disabling of PCIe ASPM options
......................................................................

soc/broadwell: Allow disabling of PCIe ASPM options

The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM)
are hardcoded for broadwell chips, but some boards may not support
these ASPM options even if the SoC does support it (non-wired CLKREQ
pin for example).
This is required to disable L1 substates on the Purism/Librem 13 which
seems to have issues with NVMe drives falling into L1.2 state and not
being able to exit that state.

Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34
Signed-off-by: Youness Alaoui 
---
M src/soc/intel/broadwell/Kconfig
1 file changed, 16 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/19899/1

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 34f515f..5132201 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -27,10 +27,6 @@
    select RELOCATABLE_RAMSTAGE
    select REG_SCRIPT
    select PARALLEL_MP
-	select PCIEXP_ASPM
-	select PCIEXP_COMMON_CLOCK
-	select PCIEXP_CLK_PM
-	select PCIEXP_L1_SUB_STATE
    select RTC
    select SMM_TSEG
    select SMP
@@ -46,6 +42,22 @@
    select HAVE_SPI_CONSOLE_SUPPORT
    select CPU_INTEL_COMMON

+config PCIEXP_ASPM
+	bool
+	default y
+
+config PCIEXP_COMMON_CLOCK
+	bool
+	default y
+
+config PCIEXP_CLK_PM
+	bool
+	default y
+
+config PCIEXP_L1_SUB_STATE
+	bool
+	default y
+
 config VBOOT
    select VBOOT_STARTS_IN_ROMSTAGE