Change in coreboot[master]: binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37192 )

Change subject: binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE
......................................................................

binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE

Direct SPI flash manipulation is forbidden, need to
go through respective FMAP and rdev APIs.

Change-Id: I765a6084fb26398008f38c0403f808bae19fdae1
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/amd/pi/Kconfig
1 file changed, 0 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37192/1

diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 828f550..d18f873 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -47,14 +47,6 @@
    hex
    default 0x10000

-config S3_DATA_POS
-	hex
-	default 0xFFFF0000
-
-config S3_DATA_SIZE
-	int
-	default 32768
-
 endif # CPU_AMD_PI

source "src/cpu/amd/pi/00630F01/Kconfig"

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37192 )

Change subject: binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE
......................................................................

Patch Set 1:

I will take the approaches from amd/stoneyridge and adapt them to both AGESA and binaryPI. Although S3 will not be supported and apparently MRC cache will not work, we want SPI flash write support for binaryPI other purposes.

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37192 )

Change subject: binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE
......................................................................

Patch Set 1: Code-Review+2

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37192 )

Change subject: binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE
......................................................................

Patch Set 2: Code-Review+2

Was it AGESA/binaryPI or coreboot operating on flash directly with this offset?
AGESA also has this defined.

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37192 )

Change subject: binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE
......................................................................

Patch Set 2:
> Patch Set 2: Code-Review+2
>
> Was it AGESA/binaryPI or coreboot operating on flash directly with this offset?
> AGESA also has this defined.

AGESA still uses this, but like I commented earlier I will pull amd/stoneyridge implementation in to use here.

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37192 )

Change subject: binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE
......................................................................

binaryPI: Drop S3_DATA_POS and S3_DATA_SIZE

Direct SPI flash manipulation is forbidden, need to
go through respective FMAP and rdev APIs.

Change-Id: I765a6084fb26398008f38c0403f808bae19fdae1
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37192
Reviewed-by: Arthur Heymans 
Reviewed-by: Michał Żygowski 
Tested-by: build bot (Jenkins) 
---
M src/cpu/amd/pi/Kconfig
1 file changed, 0 insertions(+), 8 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved
  Michał Żygowski: Looks good to me, approved

diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index ee6fa4b..d2824f2 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -51,14 +51,6 @@
    hex
    default 0x10000

-config S3_DATA_POS
-	hex
-	default 0xFFFF0000
-
-config S3_DATA_SIZE
-	int
-	default 32768
-
 endif # CPU_AMD_PI

source "src/cpu/amd/pi/00630F01/Kconfig"