Change in coreboot[master]: soc/amd/cezanne: Enable early LPC support in bootblock stage

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49929 )

Change subject: soc/amd/cezanne: Enable early LPC support in bootblock stage
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Patch Set 10:

(3 comments)

File src/soc/amd/cezanne/Kconfig:

https://review.coreboot.org/c/coreboot/+/49929/comment/7ad36335_babad728 
PS5, Line 27: 	select SOC_AMD_COMMON_BLOCK_LPC
> move this 2 lines up so it's in alphabetical order

Done

File src/soc/amd/cezanne/include/soc/acpi.h:

https://review.coreboot.org/c/coreboot/+/49929/comment/3d1f7b50_f67d0839 
PS5, Line 7: PICASSO
> CEZANNE

Done

File src/soc/amd/cezanne/include/soc/southbridge.h:

https://review.coreboot.org/c/coreboot/+/49929/comment/6a6fe40c_f1798a71 
PS5, Line 13: PM_SERIRQ_NUM_BITS
> Can you define a PM_SERIRQ_NUM_BITS_SHIFT and update all the BITS_X to have a value of 0-15

Keeping for now since it matches picasso.