Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10819
-gerrit
commit a0596a1062855c5a9598e62c45335ec0405443e4 Author: Stefan Reinauer stefan.reinauer@coreboot.org Date: Tue Jul 7 00:54:05 2015 +0200
x86: Drop -Wa,--divide
Fix up all the code that is using / to use >> for divisions instead.
Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org --- src/arch/x86/Makefile.inc | 3 --- src/cpu/amd/car/cache_as_ram.inc | 10 +++++----- src/cpu/amd/geode_gx2/cache_as_ram.inc | 2 +- src/cpu/amd/geode_lx/cache_as_ram.inc | 2 +- src/cpu/intel/car/cache_as_ram.inc | 8 ++++---- src/cpu/intel/car/cache_as_ram_ht.inc | 4 ++-- src/cpu/intel/haswell/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_2065x/cache_as_ram.inc | 4 ++-- src/cpu/intel/model_206ax/cache_as_ram.inc | 6 +++--- src/cpu/intel/model_6ex/cache_as_ram.inc | 4 ++-- src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc | 2 +- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 4 ++-- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 4 ++-- src/vendorcode/amd/agesa/f10/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f12/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f14/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f15/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f15tn/gcccar.inc | 6 +++--- src/vendorcode/amd/agesa/f16kb/gcccar.inc | 6 +++--- 19 files changed, 45 insertions(+), 48 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 20740a4..f502bbe 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -247,9 +247,6 @@ $(objgenerated)/crt0.S: $$(crt0s) # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0
-# Some cache as ram code is doing divisions -romstage-S-ccopts +=-Wa,--divide - endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64
############################################################################### diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 769e5cf..fb7c05c 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -237,15 +237,15 @@ clear_fixed_var_mtrr_out: * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4) extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12)) extractmask gas_bug_workaround, %edx /* * Without the gas bug workaround, the entire macro would consist * only of the two lines below: - * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax + * extractmask (((\carsize - \windowoffset) >> 12)), %edx */ .endm
@@ -389,7 +389,7 @@ roll_cfg: /* Calculate stack pointer. */ movl $CacheSizeAPStack, %eax mull %ebx - movl $(CacheBase + CacheSize / 2), %esp + movl $(CacheBase + CacheSize >> 1), %esp subl %eax, %esp
/* Retrive init detected. */ diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 7ddd3af..837352f 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -166,7 +166,7 @@ done_cache_as_ram_main: /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx push %esi mov $(CONFIG_DCACHE_RAM_BASE),%edi mov %edi,%esi diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index df6f942..bcb0d4b 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -192,7 +192,7 @@ done_cache_as_ram_main: * copying it back to itself to invalidate the cache */
push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx push %esi mov $(CONFIG_DCACHE_RAM_BASE),%edi mov %edi,%esi diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1d8ea8d..f9be6e8 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -195,15 +195,15 @@ clear_fixed_var_mtrr_out: * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4) extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12)) extractmask gas_bug_workaround, %edx /* * Without the gas bug workaround, the entire macro would consist * only of the two lines below: - * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax + * extractmask (((\carsize - \windowoffset) >> 12)), %edx */ .endm
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 29d7113..193ad41 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -47,7 +47,7 @@ cache_as_ram: * For hyper-threaded CPUs these are shared. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -296,7 +296,7 @@ no_msr_11e: cld xorl %eax, %eax movl $CACHE_AS_RAM_BASE, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx rep stosl
/* Enable Cache-as-RAM mode by disabling cache. */ diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 595b4df..0a070b2 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -60,7 +60,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -116,7 +116,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 62f816a..cfa3b6b 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -57,7 +57,7 @@ wait_for_sipi: post_code(0x22) /* Zero out all fixed range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -121,7 +121,7 @@ clear_var_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index f54c691..2d469ff 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -55,7 +55,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -111,7 +111,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl @@ -298,7 +298,7 @@ before_romstage: cld movl $CONFIG_RAMBASE, %esi movl CBMEM_RESUME_BACKUP, %edi - movl $HIGH_MEMORY_SAVE / 4, %ecx + movl $HIGH_MEMORY_SAVE >> 2, %ecx rep movsl
__acpi_resume_backup_done: diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index d7d932e..271b756 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -40,7 +40,7 @@ cache_as_ram:
/* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -90,7 +90,7 @@ clear_mtrrs: /* Clear the cache memory reagion. */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index 2e560d9..86c10ce 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -36,7 +36,7 @@ cache_as_ram: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx // movl $0x23322332, %eax xorl %eax, %eax rep stosl diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 7c6a67f..583ec58 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -82,7 +82,7 @@ wait_for_sipi:
/* Zero out all fixed range and variable range MTRRs. */ movl $fixed_mtrr_table, %esi - movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi + movl $((fixed_mtrr_table_end - fixed_mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx 1: @@ -152,7 +152,7 @@ wait_for_sipi: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index ba90c25..05d4889 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -63,7 +63,7 @@ wait_for_sipi: post_code(0x21) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi + movl $((mtrr_table_end - mtrr_table) >> 1), %edi xorl %eax, %eax xorl %edx, %edx clear_mtrrs: @@ -119,7 +119,7 @@ clear_mtrrs: /* Clear the cache memory region. This will also fill up the cache */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx + movl $(CACHE_AS_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl
diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index 11f50db..b0f4ee6 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -1380,7 +1380,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1389,7 +1389,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1411,7 +1411,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index f6b0899..147d16e 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1374,7 +1374,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1383,7 +1383,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1405,7 +1405,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index f0a1901..2104c27 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1388,7 +1388,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1397,7 +1397,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1419,7 +1419,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index c88709c..1ccefcf 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -1395,7 +1395,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1404,7 +1404,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1426,7 +1426,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index d6c6278..5118a4c 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1704,7 +1704,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1713,7 +1713,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1735,7 +1735,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax # diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index 90c8cc6..862c8cb 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -1069,7 +1069,7 @@ SetupStack: or %ah, %ah jne 2f # Is BSP, assign a 64K stack - mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE / 0x1000)), %ebx + mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx mov $BSP_STACK_BASE_ADDR, %ebp jmp 0f #.else # node 1 to 7, core0 @@ -1078,7 +1078,7 @@ SetupStack: mov $AMD_MTRR_FIX16k_80000, %bx shl $16, %ebx # mov %ah, %bh # Node# is used as slot# - mov $(CORE0_STACK_SIZE / 0x1000), %bl + mov $(CORE0_STACK_SIZE >> 12), %bl mov %ah, %al # Base = (Node# * Size)# mul %bl # movzx %ax, %eax # @@ -1100,7 +1100,7 @@ SetupStack: mov %al, %bh # Slot# = (CoreIndex / 16) + 4# shr $4, %bh # add $4, %bh # - mov $(CORE1_STACK_SIZE / 0x1000), %bl + mov $(CORE1_STACK_SIZE >> 12), %bl
mul %bl # Base = ( (CoreIndex * Size) ... movzx %ax, %eax #
-
Stefan Reinauer