Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)

[Arthur Heymans (Code Review)]

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Morgan Jang, Patrick Rudolph, Tim Chu.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 )

Change subject: src/intel/xeon_sp: add hardware error support (HEST)
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Patch Set 18:

(2 comments)

File src/soc/intel/common/block/acpi/acpi/globalnvs.asl:

https://review.coreboot.org/c/coreboot/+/52090/comment/d4bfc9b7_62d19d30 
PS18, Line 27: ,	8, 	// 0x40 - 0x48 Hest log buffer
> runtime ASL code does not use it.  But runtime SMM uses GNVS to retrieve the hest log address.

Ok. You might want to add a comment about this there or in the c code.

File src/soc/intel/xeon_sp/uncore.c:

https://review.coreboot.org/c/coreboot/+/52090/comment/746262da_4eda182b 
PS18, Line 149: * +--------------------------+ cbmem_top
              :  * |     HEST ELOG            | (CONFIG_ERROR_LOG_BUFFER_SIZE)
              :  * +--------------------------+
Here the HEST ELOG is below cbmem_top, but in the code it looks like it is above cbmem_top.

Is there any particular reason that HEST has to be allocated above cbmem and below DPR? This log is generated in SMM right? If it just has to be in DRAM, then allocating it in cbmem is a much better idea.