Change in coreboot[master]: mainboard/google/kahlee: Add tis_plat_irq_status

[Chris Ching (Code Review)]

Chris Ching has uploaded this change for review. ( https://review.coreboot.org/23626

Change subject: mainboard/google/kahlee: Add tis_plat_irq_status
......................................................................

mainboard/google/kahlee: Add tis_plat_irq_status

For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.

BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm

Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching 
---
M src/mainboard/google/kahlee/bootblock/bootblock.c
M src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
A src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c
M src/soc/amd/stoneyridge/Makefile.inc
4 files changed, 34 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/23626/1

diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 90c8acb..2fcf674 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -14,6 +14,7 @@
  */

#include <bootblock_common.h>
+#include <soc/gpio.h>
 #include <soc/southbridge.h>
 #include <variant/ec.h>

@@ -24,4 +25,10 @@

/* Setup TPM decode before verstage */
    sb_tpm_decode_spi();
+
+	if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) {
+		const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW |
+					GPIO_INT_STATUS_EN;
+		gpio_set_config(GPIO_9, flags);
+	}
 }
diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
index fcaf365..7213b7a 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
@@ -16,7 +16,10 @@
 bootblock-y += gpio.c
 bootblock-y += OemCustomize.c

+verstage-y += tpm_tis.c
 romstage-y += gpio.c
 romstage-y += memory.c
+romstage-y += tpm_tis.c

ramstage-y += gpio.c
+ramstage-y += tpm_tis.c
diff --git a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c
new file mode 100644
index 0000000..2ed391a
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <security/tpm/tis.h>
+#include <soc/gpio.h>
+
+int tis_plat_irq_status(void)
+{
+	return gpio_interrupt_status(GPIO_9);
+}
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 59405de..d006d5f 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -40,6 +40,7 @@
 bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
 bootblock-y += BiosCallOuts.c
 bootblock-y += bootblock/bootblock.c
+bootblock-y += gpio.c
 bootblock-y += i2c.c
 bootblock-y += monotonic_timer.c
 bootblock-y += pmutil.c
@@ -66,6 +67,7 @@
 romstage-y += tsc_freq.c
 romstage-y += southbridge.c

+verstage-y += gpio.c
 verstage-y += i2c.c
 verstage-y += monotonic_timer.c
 verstage-y += sb_util.c