Change in coreboot[master]: soc/intel/tigerlake: Add Legacy 8254 timer support

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Add Legacy 8254 timer support
......................................................................

soc/intel/tigerlake: Add Legacy 8254 timer support

This patch overrides required FSP-S UPDs to enable 8254 timer
support for TGL.

TEST=Required to boot Tiano core payload.

Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8
Signed-off-by: Subrata Banik 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39098/1

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 305748e..dbee489 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,10 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* Legacy 8254 timer support */
+	params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+	params->Enable8254ClockGatingOnS3 = 1;
+
    mainboard_silicon_init_params(params);
 }

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Add Legacy 8254 timer support
......................................................................

Patch Set 1: Code-Review+1

(3 comments)

https://review.coreboot.org/c/coreboot/+/39098/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39098/1//COMMIT_MSG@7 
PS1, Line 7: Add
Integrate

https://review.coreboot.org/c/coreboot/+/39098/1//COMMIT_MSG@10 
PS1, Line 10: support for TGL.
… if the config option is selected.

https://review.coreboot.org/c/coreboot/+/39098/1//COMMIT_MSG@12 
PS1, Line 12: Tiano core
TianoCore

Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, Sugnan Prabhu S, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39098

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
......................................................................

soc/intel/tigerlake: Integrate Legacy 8254 timer support

This patch overrides required FSP-S UPDs to enable 8254 timer
support for TGL if CONFIG_USE_LEGACY_8254_TIMER is selected.

TEST=Required to boot TianoCore payload.

Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8
Signed-off-by: Subrata Banik 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39098/2

Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
......................................................................

Patch Set 1:

(3 comments)

https://review.coreboot.org/c/coreboot/+/39098/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39098/1//COMMIT_MSG@7 
PS1, Line 7: Add
> Integrate

Ack

https://review.coreboot.org/c/coreboot/+/39098/1//COMMIT_MSG@10 
PS1, Line 10: support for TGL.
> … if the config option is selected.

Ack

https://review.coreboot.org/c/coreboot/+/39098/1//COMMIT_MSG@12 
PS1, Line 12: Tiano core
> TianoCore

Ack

Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Duncan Laurie (Code Review)]

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 139: Enable8254ClockGating
Looks like these are reserved in the stripped FSP headers, it will need to be added back for this to compile.  (why was this particular UPD sanitized in the first place?)

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 140: 1
It looks like if Enable8254ClockGating==0 but ..OnS3==1 then it will end up setting the clock gating bit on resume (from ItssLib.c).  Should these both depend on the config option?

Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 139: Enable8254ClockGating
> Looks like these are reserved in the stripped FSP headers, it will need to be added back for this to […]

we will update FSP header by EOD.

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 140: 1
> It looks like if Enable8254ClockGating==0 but .. […]

yes, make sense, will clean for other SOC as well at once

Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, Nick Vaccaro, Sugnan Prabhu S, Tim Wawrzynczak, Paul Menzel, Shelley Chen, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39098

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
......................................................................

soc/intel/tigerlake: Integrate Legacy 8254 timer support

This patch overrides required FSP-S UPDs to enable 8254 timer
support for TGL if CONFIG_USE_LEGACY_8254_TIMER is selected.

TEST=Required to boot TianoCore payload.

Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8
Signed-off-by: Subrata Banik 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/39098/3

Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 139: Enable8254ClockGating
> we will update FSP header by EOD.

Ack

https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 140: 1
> yes, make sense, will clean for other SOC as well at once

Ack

Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
......................................................................

Patch Set 4: Code-Review+1

Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
......................................................................

Patch Set 5: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: Integrate Legacy 8254 timer support

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39098 )

Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support
......................................................................

soc/intel/tigerlake: Integrate Legacy 8254 timer support

This patch overrides required FSP-S UPDs to enable 8254 timer
support for TGL if CONFIG_USE_LEGACY_8254_TIMER is selected.

TEST=Required to boot TianoCore payload.

Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39098
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Wonkyu Kim 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Wonkyu Kim: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 305748e..d22cde0 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,10 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* Legacy 8254 timer support */
+	params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+	params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
+
    mainboard_silicon_init_params(params);
 }