[M] Change in coreboot[main]: soc/intel: Allow zero values for PMC GPE0 DW registers

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Pranava Y N, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh.

Hello Dinesh Gehlot, Eran Mitrani, Eric Lai, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Pranava Y N, Sean Rhodes, Tarun, Werner Zeh, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86164?usp=email

to look at the new patch set (#7).

The following approvals got outdated and were removed:
Code-Review+1 by Matt DeVillier, Verified+1 by build bot (Jenkins)

Change subject: soc/intel: Allow zero values for PMC GPE0 DW registers
......................................................................

soc/intel: Allow zero values for PMC GPE0 DW registers

The `pmc_gpe0_different_values` function previously asserted if any
two of the GPE0 DW registers (DW0, DW1, DW2) had the same value, as
introduced in commit 640a41f3ee938b794b14 ("soc/intel: Assert if
`pmc_/gpe0_dwX` values are not unique"). This prevented platforms from
configuring GPE routing via PMC as per default register (MISCCFG) value.

This commit modifies the check to allow all DW registers to be zero.
This enables platforms that relies on MISCCFG register for
PMC-controlled GPE routing to boot without triggering the assertion.

The change was verified by testing the following scenarios:

- All DWs zero: The system boots using the default GPE route.
    No assertion occurs.
- Duplicate DWs (e.g., DW0=1, DW1=2, DW2=2): The existing assertion
    is triggered as expected.
- Unique DWs (e.g., DW0=1, DW1=2, DW2=3): No errors occur.

TEST=Built and booted normally. No assertion failure observed.

Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/pmutil.c
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/elkhartlake/pmutil.c
M src/soc/intel/jasperlake/pmutil.c
M src/soc/intel/meteorlake/pmutil.c
M src/soc/intel/pantherlake/pmutil.c
M src/soc/intel/skylake/pmutil.c
M src/soc/intel/tigerlake/pmutil.c
9 files changed, 63 insertions(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/86164/7