Change in coreboot[master]: mb/google/poppy/variant/nautilus: Correct USB OC pin configuration

[Seunghwan Kim (Code Review)]

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/27099

Change subject: mb/google/poppy/variant/nautilus: Correct USB OC pin configuration
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mb/google/poppy/variant/nautilus: Correct USB OC pin configuration

Due to schematic, we need to correct USB OC pin configuration.
 - OC0 for Type-C Port 1
 - OC1 for Type-C Port 0
 - OC2 for Type-A Port
 - OC3 to NC

BUG=NONE
BRANCH=poppy
TEST=emerge-nautilus coreboot

Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687
Signed-off-by: Seunghwan Kim 
---
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/gpio.c
2 files changed, 10 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/27099/1

diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 39d7353..79bb5fb 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -167,16 +167,16 @@
    # RP 1, Enable Latency Tolerance Reporting Mechanism
    register "PcieRpLtrEnable[0]" = "1"

-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"	# Type-A Port
+	register "usb2_ports[0]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 1
+	register "usb2_ports[1]" = "USB2_PORT_SHORT(OC2)"	# Type-A Port
    register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
+	register "usb2_ports[4]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 2
    register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)"	# H1
    register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)"	# Camera

-	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A Port
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Port
    register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Empty

# Intel Common SoC Config
diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c
index 839f425..b4db7ee 100644
--- a/src/mainboard/google/poppy/variants/nautilus/gpio.c
+++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c
@@ -231,10 +231,10 @@
    PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
    /* E10 : USB2_OC1# ==> USB3_C0_OC0_L */
    PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
-	/* E11 : USB2_OC2# ==> NC */
-	PAD_CFG_NC(GPP_E11),
-	/* E12 : USB2_OC3# ==> USB2_OC3_L */
-	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	/* E11 : USB2_OC2# ==> USB2_P2_FAULT# */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	/* E12 : USB2_OC3# ==> NC */
+	PAD_CFG_NC(GPP_E12),
    /* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */
    PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
    /* E14 : DDPC_HPD1 ==> KBC3_USB_C1_DP_HPD */