Attention is currently required from: Fred Reitberger, Jason Glenesk.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80299?usp=email )
Change subject: mb/amd/birman: add Phoenix with openSIL mainboard option ......................................................................
mb/amd/birman: add Phoenix with openSIL mainboard option
Introduce BOARD_AMD_BIRMAN_PHOENIX_OPENSIL which selects the openSIL based Phoenix SoC code. Since the Phoenix chip.c is different due to some FSP-specific data structures in there that are guarded in the openSIL case, a separate devicetree for the openSIL case is added.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I248102e92818b2d395d561a4bf2627f80906b2f7 --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/Kconfig.name R src/mainboard/amd/birman/devicetree_phoenix_fsp.cb A src/mainboard/amd/birman/devicetree_phoenix_opensil.cb 4 files changed, 155 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/80299/1
diff --git a/src/mainboard/amd/birman/Kconfig b/src/mainboard/amd/birman/Kconfig index cd7e938..9fafae1 100644 --- a/src/mainboard/amd/birman/Kconfig +++ b/src/mainboard/amd/birman/Kconfig @@ -19,6 +19,10 @@ select BOARD_AMD_BIRMAN_COMMON select SOC_AMD_PHOENIX_FSP
+config BOARD_AMD_BIRMAN_PHOENIX_OPENSIL + select BOARD_AMD_BIRMAN_COMMON + select SOC_AMD_PHOENIX_OPENSIL + config BOARD_AMD_BIRMAN_GLINDA select BOARD_AMD_BIRMAN_COMMON select SOC_AMD_GLINDA @@ -27,7 +31,7 @@
config FMDFILE default "src/mainboard/amd/birman/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_GLINDA - default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMAN_PHOENIX_FSP + default "src/mainboard/amd/birman/chromeos_phoenix.fmd" if CHROMEOS default "src/mainboard/amd/birman/board_glinda.fmd" if BOARD_AMD_BIRMAN_GLINDA default "src/mainboard/amd/birman/board_phoenix.fmd"
@@ -37,10 +41,12 @@ config MAINBOARD_PART_NUMBER default "Birman_Glinda" if BOARD_AMD_BIRMAN_GLINDA default "Birman_Phoenix_FSP" if BOARD_AMD_BIRMAN_PHOENIX_FSP + default "Birman_Phoenix_openSIL" if BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
config DEVICETREE default "devicetree_glinda.cb" if BOARD_AMD_BIRMAN_GLINDA - default "devicetree_phoenix.cb" + default "devicetree_phoenix_fsp.cb" if BOARD_AMD_BIRMAN_PHOENIX_FSP + default "devicetree_phoenix_opensil.cb" if BOARD_AMD_BIRMAN_PHOENIX_OPENSIL
config BIRMAN_HAVE_MCHP_FW bool "Have Microchip EC firmware?" diff --git a/src/mainboard/amd/birman/Kconfig.name b/src/mainboard/amd/birman/Kconfig.name index 9eee171..6daea88 100644 --- a/src/mainboard/amd/birman/Kconfig.name +++ b/src/mainboard/amd/birman/Kconfig.name @@ -3,5 +3,8 @@ config BOARD_AMD_BIRMAN_PHOENIX_FSP bool "-> Birman for Phoenix SoC using FSP"
+config BOARD_AMD_BIRMAN_PHOENIX_OPENSIL + bool "-> Birman for Phoenix SoC using openSIL" + config BOARD_AMD_BIRMAN_GLINDA bool "-> Birman for Glinda SoC" diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb similarity index 100% rename from src/mainboard/amd/birman/devicetree_phoenix.cb rename to src/mainboard/amd/birman/devicetree_phoenix_fsp.cb diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb new file mode 100644 index 0000000..58cead5 --- /dev/null +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# TODO: Update for birman + +chip soc/amd/phoenix + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x3f8, + .size = 8, + }, + .generic_io_range[1] = { + .base = 0x600, + .size = 256, + }, + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 1, + .flash_ch_en = 0, + }" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "i2c[0].early_init" = "1" + register "i2c[1].early_init" = "1" + register "i2c[2].early_init" = "1" + register "i2c[3].early_init" = "1" + + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" + + register "s0ix_enable" = "true" + + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works< + + device domain 0 on + device ref iommu on end + device ref gpp_bridge_1_1 on end # MXM + device ref gpp_bridge_1_2 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD1 + device ref gpp_bridge_1_3 on end # GBE + device ref gpp_bridge_2_1 on end # SD + device ref gpp_bridge_2_2 on end # WWAN + device ref gpp_bridge_2_3 on end # WIFI + device ref gpp_bridge_2_4 on + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end + end # NVMe SSD0 + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port2 on end + end + chip drivers/usb/acpi + device ref usb3_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port2 on end + end + chip drivers/usb/acpi + device ref usb2_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port4 on end + end + chip drivers/usb/acpi + device ref usb2_port5 on end + end + chip drivers/usb/acpi + device ref usb2_port6 on end + end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port7 on end + end + chip drivers/usb/acpi + device ref usb2_port7 on end + end + end + end + end + device ref acp on end # Audio Processor (ACP) + end + device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + device ref usb4_xhci_0 on + chip drivers/usb/acpi + device ref usb4_xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port0 on end + end + chip drivers/usb/acpi + device ref usb2_port0 on end + end + end + end + end + device ref usb4_xhci_1 on + chip drivers/usb/acpi + device ref usb4_xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port1 on end + end + chip drivers/usb/acpi + device ref usb2_port1 on end + end + end + end + end + end + end + + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on end + device ref i2c_3 on end + device ref uart_0 on end # UART0 + +end
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Felix Held (Code Review)