[XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: add ACPI code

[Jonathan Zhang (Code Review)]

Attention is currently required from: Patrick Rudolph, Simon Chou, TimLiu-SMCI, Johnny Lin, Christian Walter, Arthur Heymans, Jian-Ming Wang, Shuming Chu (Shuming).

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71967 )

Change subject: soc/intel/xeon_sp/spr: add ACPI code
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Patch Set 13:

(1 comment)

File src/soc/intel/xeon_sp/spr/romstage.c:

https://review.coreboot.org/c/coreboot/+/71967/comment/5e7a48fd_b043d389 
PS2, Line 177:  0x3F8;
> SerialIoUartDebugIoBase in FSPM_UPD is used to control the debug message from Intel FSP. […]

I think:
* Instead of hardcoding, it should be taken from CONFIG_TTYS0_BASE.
* It should be set in mainboard code, instead of SoC code.