Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83575?usp=email )
Change subject: tree: Use boolean for "eist_enable" ......................................................................
tree: Use boolean for "eist_enable"
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/lenovo/m900_tiny/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7e06/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_ehl/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/devicetree.cb M src/mainboard/purism/librem_jsl/devicetree.cb M src/mainboard/purism/librem_l1um_v2/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/tigerlake/chip.h 43 files changed, 43 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/83575/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index a33ee18..e489e25 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -16,7 +16,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 8999aa3..21661f9 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -36,7 +36,7 @@ subsystemid 0x1025 0x1037 inherit device ref system_agent on # Enable "Enhanced Intel SpeedStep" - register "eist_enable" = "1" + register "eist_enable" = "true"
# Set the Thermal Control Circuit (TCC) activation value to 97C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 92e4ba7..59e297c 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -4,7 +4,7 @@
register "deep_sx_config" = "DSX_EN_WAKE_PIN"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index f078cdf..11a8749 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -17,7 +17,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index bb896aa..ac4ec46 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -16,7 +16,7 @@ # FSP Configuration register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true"
register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 7330862..ad735ed 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -19,7 +19,7 @@ register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66"
# "Intel SpeedStep Technology" - register "eist_enable" = "1" + register "eist_enable" = "true"
# DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index db843f5..c0779c6 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -19,7 +19,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 25b8d9f..2976deb 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -16,7 +16,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# Mapping of USB port # to device #+----------------+-------+-----------------------------------+ diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 5f94e93..97b0c20 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -10,7 +10,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 74780d0..3b07bf7 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -5,7 +5,7 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */ }"
- register "eist_enable" = "1" + register "eist_enable" = "true"
device domain 0 on subsystemid 0x103c 0x2b5e inherit diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index e6655b5..51d3b26 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -6,7 +6,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 9599cec..4f7d7eb 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -7,7 +7,7 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_WAKE_PIN"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# Set the Thermal Control Circuit (TCC) activation value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index f0c8d2d..792a144 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration
- register "eist_enable" = "1" + register "eist_enable" = "true"
# Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index 65ba314..9542049 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # FSP configuration
- register "eist_enable" = "1" + register "eist_enable" = "true"
# Sagv Configuration register "sagv" = "SaGv_Enabled" diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index bc000c7..317de80 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -108,7 +108,7 @@ register "s0ix_enable" = "0"
# Enable Turbo - register "eist_enable" = "1" + register "eist_enable" = "true"
register "common_soc_config" = "{ .gspi[0] = { diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index ccfe118..613ecbf 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
register "cpu_pl2_4_cfg" = "baseline"
diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index bfb7937..df0dbdf 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -8,7 +8,7 @@ }"
register "SaGv" = "SaGv_Enabled" - register "eist_enable" = "1" + register "eist_enable" = "true"
# Enable lpss s0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 3369502..9b0357f 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -12,7 +12,7 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# Disable DPTF register "dptf_enable" = "0" diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb index cc1433d..dfacdea 100644 --- a/src/mainboard/purism/librem_cnl/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb index c992c4f..f8e494a 100644 --- a/src/mainboard/purism/librem_jsl/devicetree.cb +++ b/src/mainboard/purism/librem_jsl/devicetree.cb @@ -1,6 +1,6 @@ chip soc/intel/jasperlake
- register "eist_enable" = "1" + register "eist_enable" = "true" register "s0ix_enable" = "0"
register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb index 80c497b..e26e6b2 100644 --- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb +++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb @@ -21,7 +21,7 @@
register "s0ix_enable" = "0"
- register "eist_enable" = "1" + register "eist_enable" = "true"
register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 01ae0f2..5b448f9 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -18,7 +18,7 @@ register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# Set the Thermal Control Circuit (TCC) activaction value to 95C # even though FSP integration guide says to set it to 100C for SKL-U diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index d386397..311d96c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -5,7 +5,7 @@ register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
- register "eist_enable" = "1" + register "eist_enable" = "true"
# GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index bbc428e..cf07211 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -15,7 +15,7 @@ register "sagv" = "SaGv_Enabled"
# FSP Silicon - register "eist_enable" = "1" + register "eist_enable" = "true"
# Serial I/O register "serial_io_i2c_mode" = "{ diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 6f800cb..f35fe12 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# Graphics # IGD Displays diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 42047b2..1bf8b47 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# Graphics # IGD Displays diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 7a3f9fb..64cd913 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -4,7 +4,7 @@ register "sagv" = "SaGv_Enabled"
# FSP Silicon - register "eist_enable" = "1" + register "eist_enable" = "true" register "enable_c1e" = "1"
register "disable_dynamic_tccold_handshake" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index c29d7c9..4e8b417 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/tigerlake # CPU # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# Graphics # Not used but timings left for reference diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 2a4a21a..f5b7a1f 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -18,7 +18,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index c73bef2c..3dcc4ce 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -11,7 +11,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index dee0bf5..3a99ab4 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -18,7 +18,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index aaffd4e..ed0a520 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -18,7 +18,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index ba88a71..5760e66 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -18,7 +18,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index e4658a7..9251440 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -11,7 +11,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 4eea043..cc3c619 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -18,7 +18,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c198ea9..7e3ef0c 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -18,7 +18,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index 34105fc..4f5c72d 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -11,7 +11,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# Enable C6 DRAM register "enable_c6dram" = "1" diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 58a4fcf..2bda9dc 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -12,7 +12,7 @@
# ACPI (soc/intel/tigerlake/acpi.c) # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# CPU (soc/intel/tigerlake/cpu.c) # Power limits diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index d7a527a..d96249d 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -12,7 +12,7 @@
# ACPI (soc/intel/tigerlake/acpi.c) # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# Enable s0ix, required for TGL-U register "s0ix_enable" = "1" diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 53d5943..1c5d720 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -18,7 +18,7 @@ }"
# Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 5330f22..23a3b15 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -259,7 +259,7 @@ uint8_t Heci3Enable;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + bool eist_enable;
/* * SerialIO device mode selection: diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 7168369..32a7910 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -297,7 +297,7 @@ uint8_t skip_ext_gfx_scan;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + bool eist_enable;
/* * When enabled, this feature makes the SoC throttle when the power diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f8d4d49..35c0159 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -287,7 +287,7 @@ uint8_t SkipExtGfxScan;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + bool eist_enable;
/* Enable C6 DRAM */ uint8_t enable_c6dram;
-
Elyes Haouas (Code Review)