Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68147 )
Change subject: soc/amd/*: Hook up GPP bridges ops to devicetree ......................................................................
soc/amd/*: Hook up GPP bridges ops to devicetree
This removes the need for a PCI driver.
Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/amd/cezanne/chipset.cb M src/soc/amd/common/block/pci/pcie_gpp.c M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/picasso/chipset.cb 5 files changed, 51 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/68147/1
diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 1e3b946..3a9bd72 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -13,16 +13,17 @@ device pci 01.3 alias gpp_gfx_bridge_2 off end
device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off end - device pci 02.2 alias gpp_bridge_1 off end - device pci 02.3 alias gpp_bridge_2 off end - device pci 02.4 alias gpp_bridge_3 off end - device pci 02.5 alias gpp_bridge_4 off end - device pci 02.6 alias gpp_bridge_5 off end - device pci 02.7 alias gpp_bridge_6 off end + device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor @@ -81,12 +82,14 @@ device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B + ops amd_internal_pcie_gpp_ops device pci 0.0 alias sata_0 off ops amd_sata_ops end # first SATA controller; AHCI Mode device pci 0.1 alias sata_1 off ops amd_sata_ops end # second SATA Controller; SATA Raid/AHCI Mode device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0) device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1) end device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + ops amd_internal_pcie_gpp_ops device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio end diff --git a/src/soc/amd/common/block/pci/pcie_gpp.c b/src/soc/amd/common/block/pci/pcie_gpp.c index 2e37935..0ce3268 100644 --- a/src/soc/amd/common/block/pci/pcie_gpp.c +++ b/src/soc/amd/common/block/pci/pcie_gpp.c @@ -7,7 +7,6 @@ #include <assert.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pciexp.h> #include <soc/pci_devs.h> #include <stdio.h> @@ -48,7 +47,7 @@ acpigen_pop_len(); /* Scope */ }
-static struct device_operations internal_pcie_gpp_ops = { +struct device_operations amd_internal_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -58,21 +57,7 @@ .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, };
-static const unsigned short internal_pci_gpp_ids[] = { - PCI_DID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA, - PCI_DID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB, - PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC, - PCI_DID_AMD_FAM17H_MODELA0H_PCIE_GPP_BUSABC, - 0 -}; - -static const struct pci_driver internal_pcie_gpp_driver __pci_driver = { - .ops = &internal_pcie_gpp_ops, - .vendor = PCI_VID_AMD, - .devices = internal_pci_gpp_ids, -}; - -static struct device_operations external_pcie_gpp_ops = { +struct device_operations amd_external_pcie_gpp_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, @@ -81,17 +66,3 @@ .acpi_name = pcie_gpp_acpi_name, .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev, }; - -static const unsigned short external_pci_gpp_ids[] = { - PCI_DID_AMD_FAM17H_MODEL18H_PCIE_GPP, - PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1, - PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2, - PCI_DID_AMD_FAM17H_MODELA0H_PCIE_GPP, - 0 -}; - -static const struct pci_driver external_pcie_gpp_driver __pci_driver = { - .ops = &external_pcie_gpp_ops, - .vendor = PCI_VID_AMD, - .devices = external_pci_gpp_ids, -}; diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 3715306..139ee84 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -10,15 +10,16 @@ device pci 01.0 on end # Dummy Host Bridge
device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off end - device pci 02.2 alias gpp_bridge_1 off end - device pci 02.3 alias gpp_bridge_2 off end - device pci 02.4 alias gpp_bridge_3 off end - device pci 02.5 alias gpp_bridge_4 off end - device pci 02.6 alias gpp_bridge_5 off end + device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor @@ -65,7 +66,9 @@ device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B + ops amd_internal_pcie_gpp_ops device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID end
diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index b81890f..e000f40 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -10,15 +10,16 @@ device pci 01.0 on end # Dummy Host Bridge
device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off end - device pci 02.2 alias gpp_bridge_1 off end - device pci 02.3 alias gpp_bridge_2 off end - device pci 02.4 alias gpp_bridge_3 off end - device pci 02.5 alias gpp_bridge_4 off end - device pci 02.6 alias gpp_bridge_5 off end + device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor @@ -64,8 +65,8 @@ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.2 alias gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B - device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B + device pci 08.3 alias gpp_bridge_c ops amd_internal_pcie_gpp_ops off # Internal GPP Bridge 2 to Bus C device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID end
diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index 9a69189..756a7f4 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -9,15 +9,16 @@ device pci 00.0 alias gnb on ops picasso_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end device pci 01.0 on end # Dummy Host Bridge, do not disable - device pci 01.1 alias gpp_bridge_0 off end - device pci 01.2 alias gpp_bridge_1 off end - device pci 01.3 alias gpp_bridge_2 off end - device pci 01.4 alias gpp_bridge_3 off end - device pci 01.5 alias gpp_bridge_4 off end - device pci 01.6 alias gpp_bridge_5 off end - device pci 01.7 alias gpp_bridge_6 off end + device pci 01.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end + device pci 01.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end + device pci 01.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end + device pci 01.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 01.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias internal_bridge_a off # internal bridge to bus A + ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off end # internal GPU device pci 0.1 alias gfx_hda off end # display HD Audio controller device pci 0.2 alias crypto off end # cryptography coprocessor @@ -28,6 +29,7 @@ device pci 0.7 alias mp2 off end # sensor fusion hub (MP2) end device pci 08.2 alias internal_bridge_b off # internal bridge to bus B + ops amd_internal_pcie_gpp_ops device pci 0.0 alias sata off ops amd_sata_ops end device pci 0.1 alias xgbe_0 off end device pci 0.2 alias xgbe_1 off end
-
Arthur Heymans (Code Review)