Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38776 )
Change subject: mb/google/dedede: Add console UART configuration ......................................................................
mb/google/dedede: Add console UART configuration
Enable UART Port 2 as console UART and configure the concerned GPIOs.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 3 files changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/38776/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 9b5bd4a..c2f66a4 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -6,6 +6,7 @@ select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e98b686..4b2a3c5 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -49,7 +49,7 @@ register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoDisabled, [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }"
# Intel Common SoC Config @@ -91,7 +91,7 @@ device pci 17.0 off end # SATA device pci 19.0 off end # I2C 4 device pci 19.1 off end # I2C 5 - device pci 19.2 off end # UART 2 + device pci 19.2 on end # UART 2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index b9d77bf..c334f11 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -32,6 +32,15 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C20 : UART_DBG_TX_AP_RX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART_AP_TX_DBG_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS_N */ + PAD_NC(GPP_C22, DN_20K), + /* C23 : UART2_CTS_N */ + PAD_NC(GPP_C23, DN_20K), };
/* Early pad configuration in bootblock */
Justin TerAvest has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38776 )
Change subject: mb/google/dedede: Add console UART configuration ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38776 )
Change subject: mb/google/dedede: Add console UART configuration ......................................................................
mb/google/dedede: Add console UART configuration
Enable UART Port 2 as console UART and configure the concerned GPIOs.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I30a64a3c96226ce3244d55919b6d65fbf0a096e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38776 Reviewed-by: Justin TerAvest teravest@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c 3 files changed, 12 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Justin TerAvest: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 9b5bd4a..c2f66a4 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -6,6 +6,7 @@ select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index e98b686..4b2a3c5 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -49,7 +49,7 @@ register "SerialIoUartMode" = "{ [PchSerialIoIndexUART0] = PchSerialIoDisabled, [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }"
# Intel Common SoC Config @@ -91,7 +91,7 @@ device pci 17.0 off end # SATA device pci 19.0 off end # I2C 4 device pci 19.1 off end # I2C 5 - device pci 19.2 off end # UART 2 + device pci 19.2 on end # UART 2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index b9d77bf..c334f11 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -32,6 +32,15 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C20 : UART_DBG_TX_AP_RX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21 : UART_AP_TX_DBG_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS_N */ + PAD_NC(GPP_C22, DN_20K), + /* C23 : UART2_CTS_N */ + PAD_NC(GPP_C23, DN_20K), };
/* Early pad configuration in bootblock */
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38776 )
Change subject: mb/google/dedede: Add console UART configuration ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38776/3/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38776/3/src/mainboard/google/dedede... PS3, Line 94: on Note: If function 0 of a PCI device is disabled, then all the higher functions become disabled too. You will have to enable 19.0 as well here.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38776 )
Change subject: mb/google/dedede: Add console UART configuration ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38776/3/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38776/3/src/mainboard/google/dedede... PS3, Line 94: on
Note: If function 0 of a PCI device is disabled, then all the higher functions become disabled too. […]
nvm. I see that it is done in follow-up patch.
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Furquan Shaikh (Code Review) -
Justin TerAvest (Code Review)
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Karthik Ramasubramanian (Code Review)
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Patrick Georgi (Code Review)