Patch set updated for coreboot: 17bb610 AMD Hudson/Yangtze: Enable support for SATA port multipliers

[Bruce Griffith]

Bruce Griffith ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3808

-gerrit

commit 17bb6108351b43f5c3d9c95a0e457d6f28adf080
Author: Bruce Griffith 
Date:   Tue Jul 23 11:50:12 2013 -0600

AMD Hudson/Yangtze: Enable support for SATA port multipliers

This patch sets a bit in the Yangtze/Hudson/Bolton southbridges
    to enable the extra protocol necessary to handle port multiplier
    chips.  This has been turned on during most of Kabini development
    without any notable impact. Olive Hill has an optional daughter
    board that incorporates Silicon Image Steel Vines chips.  This
    change has been tested with and without the daughter board.  This
    change can be regression tested using any Hudson-based motherboard.

Change-Id: Ie87873b093f3e2a6a5c83b96ccb6c898d3e25f72
    Signed-off-by: Bruce Griffith 
    Reviewed-by: Martin Roth 
    Reviewed-by: Dave Frodin 
---
 src/southbridge/amd/agesa/hudson/sata.c | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c
index bc1cd92..7499370 100644
--- a/src/southbridge/amd/agesa/hudson/sata.c
+++ b/src/southbridge/amd/agesa/hudson/sata.c
@@ -29,7 +29,35 @@

static void sata_init(struct device *dev)
 {
-}
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
+	/**************************************
+	 * Configure the SATA port multiplier *
+	 **************************************/
+	#define BYTE_TO_DWORD_OFFSET(x) (x/4)
+	#define AHCI_BASE_ADDRESS_REG 0x24
+	#define MISC_CONTROL_REG 0x40
+	#define UNLOCK_BIT (1<<0)
+	#define SATA_CAPABILITIES_REG 0xFC
+	#define CFG_CAP_SPM (1<<12)
+
+	volatile u32 *ahci_ptr =
+		(u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
+	u32 temp;
+
+	/* unlock the write-protect */
+	temp = pci_read_config32(dev, MISC_CONTROL_REG);
+	temp |= UNLOCK_BIT;
+	pci_write_config32(dev, MISC_CONTROL_REG, temp);
+
+	/* set the SATA AHCI mode to allow port expanders */
+	*(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM;
+
+	/* lock the write-protect */
+	temp = pci_read_config32(dev, MISC_CONTROL_REG);
+	temp &= ~UNLOCK_BIT;
+	pci_write_config32(dev, MISC_CONTROL_REG, temp);
+#endif
+};

static struct pci_operations lops_pci = {
    /* .set_subsystem = pci_dev_set_subsystem, */