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Jérémy Compostella has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/85614?usp=email )
Change subject: soc/intel/pantherlake: Update FSPM Trace parameters
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Patch Set 1:
(2 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/85614/comment/9361ca69_904c3725?usp... :
PS1, Line 97: select SOC_INTEL_DEBUG_CONSENT # TODO: Remove the safe setting for ES SoC
we need to revert the CL which is better for the git history
+1
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/85614/comment/9df78093_25998b55?usp... :
PS1, Line 254: m_cfg->CpuCrashLogEnable = CONFIG(SOC_INTEL_CRASHLOG);
i don't see a need to do this because `SOC_INTEL_COMMON_BLOCK_TRACEHUB` is default enabled but if yo […]
I would think that now that that this non-dependency has been identified and considering the very low cost of pushing the change, we should do it.
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