Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40268 )
Change subject: mb/google/volteer: Enable RP LTR setting ......................................................................
mb/google/volteer: Enable RP LTR setting
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/40268/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 361e563..ab911d2 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -43,20 +43,24 @@
# Enable NVMe PCIE 9 using clk 0 register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0"
# Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "1"
# Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3"
# Enable WLAN PCIE 7 using clk 1 register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1"
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40268 )
Change subject: mb/google/volteer: Enable RP LTR setting ......................................................................
Patch Set 1: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40268 )
Change subject: mb/google/volteer: Enable RP LTR setting ......................................................................
Patch Set 1: Code-Review+2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40268 )
Change subject: mb/google/volteer: Enable RP LTR setting ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40268 )
Change subject: mb/google/volteer: Enable RP LTR setting ......................................................................
mb/google/volteer: Enable RP LTR setting
BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268 Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 361e563..ab911d2 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -43,20 +43,24 @@
# Enable NVMe PCIE 9 using clk 0 register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0"
# Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" register "HybridStorageMode" = "1"
# Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3"
# Enable WLAN PCIE 7 using clk 1 register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1"
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Nick Vaccaro (Code Review) -
Patrick Georgi (Code Review)
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Srinidhi N Kaushik (Code Review)
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Wonkyu Kim (Code Review)